Moon-Sang Hwang

A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method

This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers infinite input impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18-/spl mu/m four-metal mixed-mode CMOS technology. The realized active area is 0.48/spl times/0.73 mm/sup 2/. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 /spl mu/m CMOS shows <10/sup -13/ BER for 2/sup 7/-1 PRBS (pseudo-random-bit-sequence) at 5GBaud.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

A 2.5 to 10 Gb/s CMOS transceiver in 0.18 /spl mu/m CMOS dissipates 540 mW from a 1.8 V supply with a BER better than 10/sup -12/. CDR loop characteristics are stabilized across various jitter environments with small hardware overhead using an alternating edge sampling phase detector.

A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock

A referenceless, continuous-rate, fast-locking CDR with an operating range of 180 Mb/s to 3.2 Gb/s is presented. The harmonic lock property of a rotational frequency detector and the maximum run-length limit of 8B10B encoded data are utilized to detect a harmonic lock and to accelerate acquisition process. A separate VCO control scheme is introduced to stabilize the loop with a modest amount of on-chip capacitance.

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

Implemented in 0.13/spl mu/m CMOS, the 40Gb/s transmitter uses shunt-and-double-series inductive peaking and negative feedback for bandwidth enhancement and pulsed latch-based dividers and retimers for timing closure. The 38.4Gb/s 2/sup 31/-1 PRBS transmitted eye has differential voltage swing of 549mV/sub pp/, rise time of 14ps, and clock jitter of 0.65/sub rms/ and 4.9/sub pp/.

A CMOS 3.5 Gbps continuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and high-frequency boosting

This paper describes a high-speed CMOS adaptive cable equalizer with the joint adaptation method of low-frequency gain and high-frequency boosting. The adaptation method compares not only the high-frequency contents but also the low-frequency contents. By this joint adaptation method, the adaptation inaccuracy due to amplitude deviation can be reduced. The filter cell in the equalizer uses the variable-capacitor tuning and feed-forward common-mode-voltage biasing technique to achieve high bandwidth. The prototype chip is fabricated in a 0.18 /spl mu/m mixed-mode CMOS process. The realized active area is 0.48 mm/spl times/0.73 mm. The filter cell operates up to 5 Gbps and the adaptive equalizer operates up to 3.5 Gbps over a 15-m RG-58 coaxial cable with a 1.8 V supply and 80 mW power dissipation.

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

This paper describes the design and the implementation of a fully integrated 10 Gb Ethernet transceiver in a 0.13-/spl mu/m CMOS process using only a 1.2 V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver much simpler. The test chip consumes 898 mW from a 1.2 V supply.

A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits

This paper describes a quad 3.125 Gbps transceiver focusing on digital data recovery circuits. Effect of each design parameters on jitter tolerance (JTOL) is analyzed and for better JTOL, a new phase-averaging method with internal forward path is proposed. On-chip JTOL measurement circuits are implemented to characterize the transceiver performance, and it shows that the proposed method improves the JTOL about 0.1 UI. Implemented in 0.13 CMOS, the transceiver tolerates up to 0.67 UI of total jitter at 3.125Gbps.

A fully integrated 0.13 /spl mu/m CMOS 10 Gb Ethernet transceiver with XAUI interface

A 10 Gb Ethernet transceiver chip integrated with 10 Gb/s serial and quad 3.125 Gb/s XAUI interfaces is implemented in 0.13 /spl mu/m CMOS and dissipates 898 mW from 1.2 V. A digital coarse control algorithm for VCOs reduced the VCO gains for noise immunity. A blind oversampling technique enabled synthesis of the XAUI interface.