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Dive into the research topics where Yoni Aizik is active.

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Featured researches published by Yoni Aizik.


IEEE Computer | 2016

H-EARtH: Heterogeneous Multicore Platform Energy Management

Efraim Rotem; Uri C. Weiser; Avi Mendelson; Ran Ginosar; Eliezer Weissmann; Yoni Aizik

By scheduling each workload according to its most advantageous core and managing voltage and frequency, the heterogeneous energy-aware race to halt (H-EARtH) algorithm optimizes CPU platform energy.


great lakes symposium on vlsi | 2010

Challenges and methodologies for efficient power budgeting across the die

Pinkesh J. Shah; Yoni Aizik; Muhammad K. Mhameed; Gila Kamhi

To provide higher performance by staying within a constant power budget is challenging. Today, operational cost and specifically energy cost constitute a large portion of an organizations Total Cost of Ownership (TCO), so it is crucial that microprocessor consumes the lowest possible power for a given workload. In this paper, we describe the major challenges faced by the microprocessor architects in achieving higher performance within constant power budget or energy-efficiency, with special focus on design technologies and solutions. We present a die level power simulation solution that facilitates exploration of system-level power management algorithms that budget power for various microprocessor die components. We demonstrate usage methodology via real-life use case studies and recommend future areas of research that can enhance the proposed power management simulation methodology.


power and timing modeling optimization and simulation | 2009

Power-Aware Design via Micro-architectural Link to Implementation

Yoni Aizik; Gila Kamhi; Yael Zbar; Hadas Ronen; Muhammad Abozaed

Micro-architectural power macro-models dictate the power budget of a new chip design. Based on the early feasibility studies, power specification of new features are defined and then verified all through the design cycle. In this paper, we introduce a novel power-aware design paradigm that aligns power macro-models by mapping power-significant events at all levels of design hierarchy. We apply this paradigm on a state-of-the-art 65nm high-performance micro-processor and demonstrate significant benefits in power optimization at RTL implementation.Moreover, this approach facilitates a feedback loop from the design implementation to higher level (micro-architectural) power models and thus has built-in potential for more accurate power models.


Archive | 2015

Forcing a processor into a low power state

Eliezer Weissmann; Yoni Aizik; Doron Rajwan; Nir Rosenzweig; Efraim Rotem; Barnes Cooper; Paul S. Diefenbaugh; Guy M. Therien; Michael Mishaeli; Nadav Shulman; Ido Melamed; Niv Tokman; Alexander Gendler; Arik Gihon; Yevgeni Sabin; Hisham Abu Salah; Esfir Natanzon


Archive | 2014

METHOD AND APPARATUS FOR DETERMINING THREAD EXECUTION PARALLELISM

Eliezer Weissmann; Arik Gihon; Efraim Rotem; Paul S. Diefenbaugh; Eric C. Samson; Michael Mishaeli; Yoni Aizik; Chen Ranel


Archive | 2014

Optimization of energy usage in a processor

Yoni Aizik; Eliezer Weissmann; Efraim Rotem; Yevgeni Sabin; Doron Rajwan; Ahmad Yasin


Archive | 2016

Controlling performance states of processing engines of a processor

Eliezer Weissmann; Efraim Rotem; Hisham Abu Salah; Yoni Aizik; Doron Rajwan; Nir Rosenzweig; Gal Leibovich; Yevgeni Sabin; Shay Levy


Archive | 2015

TECHNIQUES FOR FLEXIBLE AND DYNAMIC FREQUENCY-RELATED TELEMETRY

Doron Rajwan; Eliezer Weissmann; Yoni Aizik; Itai Feit; Tal Kuzi; Tomer Ziv; Nadav Shulman


Archive | 2014

Processor operating by selecting smaller of requested frequency and an energy performance gain (EPG) frequency

Yoni Aizik; Eliezer Weissmann; Efraim Rotem; Yevgeni Sabin; Doron Rajwan; Ahmad Yasin


Archive | 2013

Systememulation für benutzerereignisse/-verhaltensweisen und wahrnehmungsberechnungen

Gila Kamhi; Amit Moran; Limor David; Yoni Aizik

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