Yoshiaki Deguchi
Chuo University
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Publication
Featured researches published by Yoshiaki Deguchi.
international reliability physics symposium | 2016
Yoshiaki Deguchi; Tsukasa Tokutomi; Ken Takeuchi
Read-disturb Modeled LDPC (RDM-LDPC) ECC is proposed. Conventional Advanced Error-Prediction LDPC (AEP-LDPC) [1] corrects data-retention errors of data-storage-purpose SSDs storing photos, movies, etc. but cannot correct read-disturb errors. For read-intensive computing-purpose enterprise SSDs, this paper analyzes the read-disturb errors, develops the error model of 1Xnm TLC NAND Flash memory and proposes ECC suitable for read-disturb errors. It is experimentally demonstrated that proposed RDM-LDPC extends the read cycle of SSDs by 5000-times.
symposium on vlsi technology | 2017
Yoshiaki Deguchi; Atsuro Kobayashi; Hikaru Watanabe; Ken Takeuchi
Highly reliable data compression technique. Flash Reliability Boost Huffman coding (FRBH) is proposed for TLC NAND Flash memory. By decreasing the write data size and optimizing the memory cell Vth distribution at the same time, FRBH decreases data-retention errors by 92% and increases data-retention time by over 2900 times.
international memory workshop | 2017
Toshiki Nakamura; Yoshiaki Deguchi; Ken Takeuchi
To improve the reliability of Triple-Level Cell (TLC) NAND flash memory, Advanced Error Prediction (AEP) low-density parity-check (LDPC) ECC with Error Dispersion Coding is proposed. In the conventional LDPC, error-correction capability is degraded due to burst errors [1]. To reduce burst errors and improve the error-correction capabilities of LDPC, this paper proposes Error Dispersion Coding (EDC) which reduces burst errors, decreases the worst bit-error rate (BER) of Upper/Middle/Lower pages, and finally extends the data-retention time of TLC NAND flash memory. By applying proposed EDC, in 3D-TLC NAND flash memory, the burst errors and the worst BER are decreased by 87% and 40%, respectively. As a result, the acceptable data-retention time is extended by 1.8 and 2.6 times in 2D and 3D-TLC NAND flash memory, respectively.
custom integrated circuits conference | 2017
Yoshiaki Deguchi; Toshiki Nakamura; Atsuro Kobayashi; Ken Takeuchi
Value-Aware SSD with Vertical 3D-TLC (Triple-Level Cell) NAND flash for the image recognition is proposed to increase the acceptable bit-error rate (BER) by 12-times and extend the data-retention time by 300-times. In addition to the reliability improvement, the read time reduces by 26%. The proposed SSD combines new data-aware techniques with deep neural networks error tolerance. 10% BER of NAND flash is allowed while providing the accurate and fast image recognition. The design overhead in the SSD controller is negligibly small.
international symposium on circuits and systems | 2018
Atsuna Hayakawa; Toshiki Nakamura; Yoshiaki Deguchi; Kazuki Maeda; Ken Takeuchi
international symposium on circuits and systems | 2018
Keita Mizushina; Toshiki Nakamura; Yoshiaki Deguchi; Ken Takeuchi
international reliability physics symposium | 2018
Shun Suzuki; Yoshiaki Deguchi; Toshiki Nakamura; Kyoji Mizoguchi; Ken Takeuchi
international memory workshop | 2018
Yoshiaki Deguchi; Kazuki Maeda; Shun Suzuki; Toshiki Nakamura; Ken Takeuchi
international memory workshop | 2018
Yoshiaki Deguchi; Ken Takeuchi
european solid state device research conference | 2018
Shun Suzuki; Yoshiaki Deguchi; Toshiki Nakamura; Ken Takeuchi