Toshiki Nakamura

A novel gate-offset NAND cell (GOC-NAND) technology suitable for high-density and low-voltage-operation flash memories

This paper describes a novel scaled and low-voltage-operation NAND EEPROM technology with a G_ate-O_ffset NAND C_ell (GOC-NAND), which is free from program disturbance in a self-boosted program. In GOC-NAND, novel source/drain engineering is introduced for the first time. The program disturbance is decreased by two decades of magnitude in 0.1 /spl mu/m generation, without area penalty and additional process steps. Furthermore, the program disturbance is not increased by scaling and low voltage operation. Therefore, GOC-NAND is indispensable technology for gigabit-scaled NAND EEPROMs.

AEP-LDPC ECC with Error Dispersion Coding for Burst Error Reduction of 2D and 3D NAND Flash Memories

To improve the reliability of Triple-Level Cell (TLC) NAND flash memory, Advanced Error Prediction (AEP) low-density parity-check (LDPC) ECC with Error Dispersion Coding is proposed. In the conventional LDPC, error-correction capability is degraded due to burst errors [1]. To reduce burst errors and improve the error-correction capabilities of LDPC, this paper proposes Error Dispersion Coding (EDC) which reduces burst errors, decreases the worst bit-error rate (BER) of Upper/Middle/Lower pages, and finally extends the data-retention time of TLC NAND flash memory. By applying proposed EDC, in 3D-TLC NAND flash memory, the burst errors and the worst BER are decreased by 87% and 40%, respectively. As a result, the acceptable data-retention time is extended by 1.8 and 2.6 times in 2D and 3D-TLC NAND flash memory, respectively.

12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition

Value-Aware SSD with Vertical 3D-TLC (Triple-Level Cell) NAND flash for the image recognition is proposed to increase the acceptable bit-error rate (BER) by 12-times and extend the data-retention time by 300-times. In addition to the reliability improvement, the read time reduces by 26%. The proposed SSD combines new data-aware techniques with deep neural networks error tolerance. 10% BER of NAND flash is allowed while providing the accurate and fast image recognition. The design overhead in the SSD controller is negligibly small.