Fumiko Iwao

Advanced resist process enabling implementation of CD controllability for 32 nm and beyond

Exposure wavelength has been changing dramatically as semiconductor design rules shrink, and for 32nm-node fine processes and beyond, it is predicted that the drop in optical contrast when using 193nm immersion lithography exposure technology will make it difficult to ensure good resolution performance in fine and dense resist patterns. To address this problem, studies have begun on extreme ultraviolet (EUV) lithography technology and double patterning technology that uses 193nm immersion lithography as alternative technologies, but many problems have been reported at the present stage of development. Against the above background, we investigated various process flows with the aim of reducing production processes and cost in double patterning technology that uses 193nm immersion lithography. We consequently developed an advanced process technique for use after 1st resist pattern formation and established a litho-litho-etch (LLE) process. The application of this technology decreases the number of total processes used in ordinary double patterning technology. In this paper, we focus on double patterning technology in 193nm immersion lithography and report on the performance of our original advanced process technique and on our evaluation of double patterning technology.

Fabrication of 22-nm poly-silicon gate using resist shrink technology

Exposure wave length has been changing rapidly with the shrink of design rule. In 32nm node and beyond, it is predicted that keeping good resolution performance of resist pattern with small dimension and high density will be more difficult due to the drop of optical contrast in 193nm immersion lithography. EUV lithography and Double Patterning using 193nm immersion lithography are being investigated as alternative technologies, but it is currently difficult to keep enough process margins in device fabrication. Resist slimming technology by dry process and exposure process is also being investigated based on these technical backgrounds but many technical challenges have been reported. We started to develop our original resist slimming technology in track process with the aim of overcoming technical challenges and cost reduction, which is one of main challenges in double pattering. In this paper, we report the basic characteristics of our resist slimming process (controllability of CD shrink, CD uniformity within wafer, LWR, and total process margin) and also pattern transfer performance of CD and LWR after dry etching in order to apply this slimming technology to Double Pattering.

Driving DSA into volume manufacturing

Directed Self-Assembly (DSA) is being extensively evaluated for application in semiconductor process integration.1-7 Since 2011, the number of publications on DSA at SPIE has exploded from roughly 26 to well over 80, indicating the groundswell of interest in the technology. Driving this interest are a number of attractive aspects of DSA including the ability to form both line/space and hole patterns at dimensions below 15 nm, the ability to achieve pitch multiplication to extend optical lithography, and the relatively low cost of the processes when compared with EUV or multiple patterning options. Tokyo Electron Limited has focused its efforts in scaling many laboratory demonstrations to 300 mm wafers. Additionally, we have recognized that the use of DSA requires specific design considerations to create robust layouts. To this end, we have discussed the development of a DSA ecosystem that will make DSA a viable technology for our industry, and we have partnered with numerous companies to aid in the development of the ecosystem. This presentation will focus on our continuing role in developing the equipment required for DSA implementation specifically discussing defectivity reduction on flows for making line-space and hole patterns, etch transfer of DSA patterns into substrates of interest, and integration of DSA processes into larger patterning schemes.

High-etching selectivity of spin-on-carbon hard mask process for 22nm node and beyond

As part of the trend toward finer semiconductor design rules, the resist film thickness is getting thinner, and the etching technology that uses resist masking is getting more difficult. To solve such a problem in recent years, the film structure used in the resist process also is changing from the single-layer process (BARC and resist stacked film) to the multi-layer process (Carbon hard-mask, middle layer and resist stacked film) The carbon hard-mask of multi-layer process can be divided into two kinds, which are the CVD-carbon (CVD-C) that uses the chemical vapor deposition method and Spin-on-carbon (SOC) that uses the spin-coating method. CVD-C is very attractive for ensuring the high etching selection ratio, but still has major challenges in particle reduction, lower planarization of substrate and high process cost. On the other hand, SOC is very attractive for low cost process, high level of planarization of substrate and no particles. Against this background, we verify the development of the SOC that had the high etch selection ratio by improving etching condition, material and SOC cure condition. Moreover, we can fabricate below 30nm SiO2 patterning and the possibility of development with extreme ultraviolet lithography (EUVL) was suggested. This paper reports on the results of a comprehensive process evaluation of a SOC based multi-layer technology using lithography clusters, etching tools.

Important challenges for line-width-roughness reduction

It is supposed that double patterning process is one of the promising candidates for making mask pattern for dry etching at 32nm and 22nm node. Currently, drastic improvement of overlay of scanner is considered to be the most important challenge and much attention has been paid to sidewall spacer process since it can avoid that problem and also can provide easier method to fabricate patterns repeatedly. In this paper, material option of core pattern, spacer pattern and hard mask, which are main components of this process, is presented and 32nm gate pattern is actually fabricated after process optimization. In addition, line-width-roughness (LWR), whose reduction is becoming more and more necessary, is measured in each process step of spacer process.

Fabrication of 32-nm contact/via hole by photolithographic-friendly method

As semiconductor design rules continue to shrink, studies have begun on the 32nm-node and 22nm-node generations in semiconductor lithography technology in conjunction with the development of various fine-processing technologies. Research has been especially active in the development of high-NA193nm immersion lithography and EUV lithography for 32nm processes and beyond, but at the present stage of development, many technical issues have been reported. For example, in the contact-hole and via-hole pattern formation process in 193nm immersion lithography, it is difficult to maintain good resolution performance and process margins compared to line and space patterns. Poor resolution and other defects in the lithography process are major factors behind reduced yields in semiconductor production lines, and to prevent such defects, studies have begun on double patterning technology and shrink technology applied after resist-hole-pattern formation. Here, however, the need for reducing production processes and production costs have become major issues. In response to these technical issues, we evaluated a variety of hole-shrink processes as candidates for a fine-hole-pattern formation technology, and as a result of this study, we succeeded in applying an original hole-shrink technology to the formation of 40nm hole patterns and beyond.

Availability of underlayer application to EUV process

EUV lithography is one of the most promising technologies for the fabrication of beyond 30nm HP generation devices. However, it is well-known that EUV lithography still has significant challenges. A great concern is the change of resist material for EUV resist process. EUV resist material formulations will likely change from conventional-type materials. As a result, substrate dependency needs to be understood. TEL has reported that the simulation combined with experiments is a good way to confirm the substrate dependency. In this work the application of HMDS treatment and SiON introduction, as an underlayer, are studied to cause a footing of resist profile. Then, we applied this simulation technique to Samsung EUV process. We will report the benefit of this simulation work and effect of underlayer application. Regarding the etching process, underlayer film introduction could have significant issues because the film that should be etched off increases. For that purpose, thinner films are better for etching. In general, thinner films may have some coating defects. We will report the coating coverage performance and defectivity of ultra thin film coating.

Implementation of double patterning process toward 22-nm node

In the field of photolithography, a variety of resolution enhancement techniques (RETs) are being applied under the mainstream technology of 193-mm water-based immersion lithography. The resolution performance of photoresist, however, is limited at 40 nm. Double patterning (DP) is considered to be an effective technology for overcoming this limiting resolution. Many double-patterning techniques have come to be researched such as litho-etch-litho-etch (LELE), litho-litho-etch (LLE), and self-aligned spacer DP, but as the pattern-splitting type of double patterning requires high overlay accuracy in exposure equipment, the self-aligned type of double patterning has become the main approach. This paper introduces the research results of various double-patterning techniques toward 22nm nodes and touches upon newly developed elemental technologies for double patterning.