Yoshikazu Saitoh

16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors

A 16 Mb SRAM based on an electric-field-relaxed scheme and an alternate error checking and correction architecture for handling cosmic-ray-induced multi-errors is realized in 0.13 /spl mu/m CMOS technology. The IC has a 16.7 fA/cell standby current, a cell size of 2.06 /spl mu/m/sup 2/ and a 99.5% smaller SER.

SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect

This paper describes an investigation of cosmic-ray-induced multicell error behavior in SRAMs. A combination of device- and circuit-level simulation was used to show that a parasitic bipolar effect is responsible for such errors, and the underlying mechanism is what we call a battery effect. We have also demonstrated, for the first time, that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well taps (Nc). The results are used as the basis of an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multicell errors. The proposed guideline simply states that the allocation of memory cells to addresses should be based on consideration of the Nc. The architecture in its form reduces the soft error rate of an SRAM with Nc=16 by 88%.

Cosmic-ray multi-error immunity for SRAM, based on analysis of the parasitic bipolar effect

This paper describes an investigation of cosmic-ray-induced multi-cell error (MCE) behavior in SRAMs through device- and circuit-level simulation methods developed on the basis that a parasitic bipolar effect is responsible for such errors. The first demonstration that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well contacts (Nc) is presented. The results are applied in an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multi-cell errors. A new architecture is proposed, in which matching of addresses to memory cells is consideration of the Nc. This architecture reduced soft error rate (SER) for an SRAM fabricated by using 0.13-/spl mu/m CMOS technology by 88%.

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS. The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C. Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell. As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell. We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability. By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability.

A 0.13-/spl mu/m, 0.78-/spl mu/m/sup 2/ low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

We developed a four-transistor SRAM cell with a vertically stacked poly-silicon MOS. Its size-fabricated by using 0.13-/spl mu/m technology - is 0.78 /spl mu/m/sup 2/, that is, only 38% of that of a six-transistor SRAM cell. By optimizing the threshold voltages and the gate-oxide thicknesses of the cell transistors, and developing a modified electric-field-relaxation scheme, an estimated cell leakage current of 88.7 fA/cell was achieved. We also developed a dual-word-voltage scheme to achieve stable operation of the cell during a read operation without affecting a write operation.