Shiro Kamohara

Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies

Random threshold voltage (VM) fluctuation data obtained from multiple fabs, generations and technologies, as well as theoretical / TCAD results are carefully compared using a special normalization method. It is revealed that P-FET fluctuation can be almost fully accounted for by dopant fluctuation regardless of device generations and designs, whereas extra fluctuation mechanism(s) significantly contributes to N-FETs.

The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories

This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory. We acquired large-scale data of Vth fluctuation and confirm the existence of the tail bits generated by RTS. The amount of Vth broadening due to the tail bits becomes larger as the scaling advances, and reaches to more than 0.3 V in 45-nm node. Thus the RTS becomes prominent issue for the design of multilevel flash memory in 45-nm node and beyond

Anomalously Large Threshold Voltage Fluctuation by Complex Random Telegraph Signal in Floating Gate Flash Memory

A threshold voltage fluctuation (DeltaVth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the DeltaVth, we found an anomalously large DeltaVth at high percentage region of the DeltaVth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion of the DeltaVth distribution increases after program/erase (P/E) cycle. Since the DeltaVth due to the complex RTS is much larger than the simple RTS, the complex RTS become one of the reliability issues in larger capacity flash memory, especially after P/E cycle

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.

Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array

Noise margin, characteristics of six individual cell transistors, and their variability in static random-access memory (SRAM) cells are directly measured using a special device-matrix-array test element group of 16-kb SRAM cells, and the correlation between the SRAM noise margin and the cell transistor variability is analyzed. It is found that each cell shows a very different supply voltage Vdd dependence of the static noise margin (SNM), and this scattered Vdd dependence of the SNM is not explained by the measured threshold voltage Vth variability alone, indicating that the circuit simulation taking only the Vth variability into account will not predict the SRAM stability precisely at low supply voltage.

A new data retention mechanism after endurance stress on flash memory

We propose a new data retention model after endurance stress that may be explained as a combination of two retention mechanisms. One inherent retention characteristic is ruled by thermionic emission and is dominant above 150 C. The other retention mechanism is dominant below 85 to 125 C and is controlled by anomalous SILC. We have clarified that the data retention properties after P/E cycling were well fitted by the hopping conduction model. In particular, the presence of traps generated by excessive P/E cycling played a significant role in the temperature dependence of the retention lifetime.

Impact of DIBL variability on SRAM static noise margin analyzed by DMA SRAM TEG

The static noise margin (SNM) as well as V<inf>th</inf>, g<inf>m</inf>, body factor, and drain-induced-barrier-lowering (DIBL) in individual transistors in SRAM cells are directly measured by 16k bit device-matrix-array (DMA) SRAM TEG. It is found that, besides V<inf>th</inf> variability, DIBL variability degrades SRAM stability and its V<inf>dd</inf> dependence while the variability of g<inf>m</inf> and body factor has only a small effect.

Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection

The lateral profile of trapped charge in a silicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory programmed using channel-hot-electron injection is determined using current-voltage (I/sub D/-V/sub G/) measurements along with two-dimensional device simulations and is verified using gate-induced-drain-leakage measurements, charge-pumping (CP) measurements, and Monte Carlo simulations. An iterative procedure is used to match simulated I/sub D/-V/sub G/ characteristics with experimental I/sub D/-V/sub G/ characteristics at different stages of programming, by sequentially increasing the trapped electron charge in simulations. Fresh cells are found to contain a high laterally nonuniform trapped charge, which (along with large electron injection during the program) make the conventional CP techniques inadequate for extracting the charge profile. This charge results in a nonmonotonous variation of threshold and flat-band voltages along the channel and makes it impossible to simultaneously determine interface and trapped charge profiles using CP alone. The CP technique is modified for application to SONOS cells and is used to verify the charge profile obtained using I/sub D/-V/sub G/ and to estimate the interface degradation. This paper enhances the study presented in our earlier work.

Analyses of 5σ V th fluctuation in 65nm-MOSFETs using takeuchi plot

Using 1M DMA-TEG, the analyses of 5sigma Vth fluctuation in 65 nm-MOSFETs were carried out. Physical and electrical analyses confirmed that random dopant fluctuation is dominant though NMOSFET has larger fluctuation as compared with PMOSFET. To explain this phenomenon, a B clustering model is proposed. In the case of clustering with 5 to 6 B atoms in the channel, Vth fluctuation of NMOSFET can be explained.

Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors

A very rapid method of estimating the effect of gate-edge fluctuation on threshold voltage (Vth) variability in metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. An empirical model is developed, in which correlation width (Wc) from gate line-width roughness (LWR) is a key parameter of the model. The validity of the model is confirmed using the measured data and an autoregressive model. Wc is extracted from the gate line-edge shape depicted in a scanning electron microscope (SEM) image. This method is very useful for the intuitive understanding of the gate-edge fluctuation effect on Vth variability.