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Dive into the research topics where Yoshinori Shirakawa is active.

Publication


Featured researches published by Yoshinori Shirakawa.


custom integrated circuits conference | 2009

A 14.6 th -order 3.456GHz transmit baseband filter in 110nm CMOS for millimeter-wave communication systems

Michiko Tokumaru; Heiji Ikoma; Yuji Yamada; Kouji Okamoto; Akira Yamamoto; Yoshinori Shirakawa

This paper presents a 1.728Gbps transmit baseband filter for transmitters of millimeter-wave communication systems. In order to avoid the inter symbol interference, ultra wide band and very high order filter is demanded. It is impracticable to realize such a high order filter with conventional analog technique, such as gm-C filter. The proposed filter consists of a 3.456GHz digital filter followed by an 8-bit 3.456Gsps digital to analog converter (DAC), which occupies 0.265mm2 in 110nm CMOS processes. It is difficult to adjust the clock and data delay at 3.456GHz. The DAC has a clock divider for the high speed operation. The new filter consumes 142mW and achieves the transmit spectrum very close to the mask regulated by IEEE802.15.3c.


Japanese Journal of Applied Physics | 2008

Quasi-Synchronous Sampling and Adaptive Partial-Response Maximum-Likelihood Read-Channel System

Akira Yamamoto; Yoshinori Shirakawa; Hiroki Mouri; Kouji Okamoto; Kouichi Nagano; Hiroyuki Nakahira; Takashi Yamamoto

We propose a read-channel system with quasi-synchronous sampling and an adaptive partial-response maximum-likelihood (PRML) method to achieve accurate timing recovery and correct data extraction under high-density recording with a high transfer rate. The proposed system can extract data correctly in the state of either oversampling or undersampling using first-in-first-out flip-flops (FIFOs) and an asynchronously sampled data processable maximum-likelihood detector (ASML). In other words, it allows a sampling clock to be incompletely synchronized with a channel bit. Furthermore, the ASML adaptively learns the references required for calculating branch metrics even though the input data are not synchronized with the channel bit. This system achieves stable data extraction under quasi-synchronous sampling, improves the bit-error-rate performance, and can be applied to next-generation, high-density, and high-transfer-rate storage systems.


international solid-state circuits conference | 2013

A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications

Noriaki Saito; Takayuki Tsukizawa; Naganori Shirakata; Tadashi Morita; Koichiro Tanaka; Junji Sato; Yohei Morishita; Masaki Kanemaru; Ryo Kitamura; Takahiro Shima; Toshifumi Nakatani; Kenji Miyanaga; Tomoya Urushihara; Hiroyuki Yoshikawa; Takenori Sakamoto; Hiroyuki Motozuka; Yoshinori Shirakawa; Naoya Yosoku; Akira Yamamoto; Ryosuke Shiozaki; Koji Takinami


Archive | 2011

RECEIVER AND TRANSMISSION/RECEPTION SYSTEM

Akira Yamamoto; Kouji Okamoto; Yoshinori Shirakawa


Archive | 2014

RECEPTION APPARATUS, PHASE ERROR ESTIMATION METHOD, AND PHASE ERROR CORRECTION METHOD

Yoshinori Shirakawa; Koichiro Tanaka; Takenori Sakamoto


Archive | 2011

RECEIVER, SIGNAL PROCESSING APPARATUS, AND VIDEO DISPLAY APPARATUS

Akira Yamamoto; Kouji Okamoto; Yoshinori Shirakawa


Archive | 2007

REPRODUCED SIGNAL PROCESSOR AND VIDEO DISPLAY

Kouji Okamoto; Akira Yamamoto; Hiroki Mouri; Yoshinori Shirakawa


Archive | 2008

PHASE COMPARATOR, PLL CIRCUIT, INFORMATION REPRODUCTION PROCESSING DEVICE, OPTICAL DISK PLAYBACK DEVICE AND MAGNETIC DISK PLAYBACK DEVICE

Akira Yamamoto; Yoshinori Shirakawa; Kouji Okamoto; Hiroki Mouri


Archive | 2009

Phase comparator, pll circuit, information regeneration processing apparatus, optical disc regenerating apparatus, and magnetic disc regenerating apparatus

Akira Yamamoto; Yoshinori Shirakawa; Kouji Okamoto; Hiroki Mouri


Archive | 2007

REPRODUCTION SIGNAL PROCESSING DEVICE AND VIDEO DISPLAY DEVICE

Yoshinori Shirakawa; Akira Yamamoto

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