Takenori Sakamoto

A 60GHz wireless transceiver employing hybrid analog/digital beamforming with interference suppression for multiuser gigabit/s radio access

This paper presents a 60GHz analog/digital beamforming transceiver that effectively suppresses interference signals, targeting WiGig/IEEE 802.11ad standard. A prototype has been built with 40nm CMOS analog front-ends as well as offline baseband digital signal processing. Measurement shows 3.1dB EVM advantage over the conventional two-stream diversity during a packet collision situation.

A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS

This paper presents an LDPC decoder employing a column-parallel architecture that enables low-power and high-speed operation suitable for the 802.11ad standard. As compared to the conventional row-parallel architecture, the proposed architecture reduces the required memory size by 60% and also minimizes the number of pipeline stages for high throughput operation. Fabricated in 40nm LP CMOS technology, the prototype achieves high energy efficiency of 4.7pJ/bit/iteration for 6.16Gb/s while supporting all the modulation and coding schemes (MCS0 to MCS12) required for the 802.11ad single-carrier (SC) modulation.