Yoshio Kohno

A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

A 128-kb word/spl times/8-b CMOS SRAM with an access time of 3 ns and a standby current of 2 /spl mu/A is described. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-/spl mu/m minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transition detection (ATD) are used. This RAM has a flash-clear function in which logical zeros are written into all memory cells in less than 1 /spl mu/s.

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.

An asymmetric memory cell using a C-TFT for ULSI SRAMs

A compact SRAM memory cell structure using a set of C-TFTs (complementary thin-film transistors) is discussed. A C-TFT is composed of a top-gate N-channel TFT and a bottom-gate P-channel TFT. The proposed cells size was reduced to 80% of that of a conventional one at the 16-Mb SRAM level. Also, a stable read operation under a low-supply voltage could be realized by using a C-TFT.<<ETX>>

A large cell-ratio and low node leak 16 M-bit SRAM cell using ring-gate transistors

An advanced memory cell for a 16-Mb SRAM (static RAM) has been developed. The cell has ring-shaped gate electrode (ring-gate) driver transistors and PMOS TFT (thin film transistor) loads utilizing steps of underlayers. The ring-gate driver transistors achieve more than 3.2 large cell-ratio ( beta r) which is free from misregistration, and also 2-fA low-leakage current of the memory cell node. The titanium silicided source region (Rs=7 Omega / Square Operator ) of driver transistors is common to both in a cell, so there is little imbalance of the ground line. The 14-fA off-current (Vd=3 V, Vg=0 V) of the TFT makes possible less than 0.3- mu A standby current in a 16-Mb SRAM. It is noted that these device characteristics will certainly make it possible to fabricate a 16-Mb SRAM with this cell.<<ETX>>

A 45-ns 256K CMOS static RAM with a tri-level word line

A 32K words by 8-bit static RAM fabricated with a CMOS technology is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1.3-/spl mu/m design rule allowed layout of the NMOS memory cell in an area of 116.0 /spl mu/m/SUP 2/ and the die in 49.6 mm/SUP 2/.

A high performance 0.6 mu m BiCMOS SRAM technology with emitter-base self-aligned bipolar transistors and retrograde well for MOS transistors

The described technology uses a quintuple poly-Si and double-metal process architecture. The emitter and base of a bipolar transistor are self-aligned. The retrograde well for MOS transistors and the P isolation for bipolar transistors are formed by using high-energy ion implantation, while the concentration of the collector is determined by an N epitaxial layer only. As thick oxide remains at the base region before sidewall formation of MOS transistors, an ideal base current flows. The delay times of ECL, CMOS, and BiNMOS are 87 ps, 97 ps, and 130 ps, respectively. BiNMOS has a speed advantage over CMOS down to 2.5 V. A 5-ns 256 K (32 K*8) TTL SRAM has been fabricated with a 0.6- mu m BiCMOS SRAM technology.<<ETX>>

A 4.5ns 256K CMOS SRAM with tri-level word line

A report on a CMOS SRAM with a peak current of 45mA obtained through the use of an address transition activated circuit combined with a tri-level word-line circuit will be presented.

An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-/spl mu/m design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT.

A fast 8K &#215; 8 mixed CMOS static RAM

This paper describes a fast 8K × 8 static RAM fabricated with a mixed CMOS technology. To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard bands around the wells. A 2-µm design rule combined with the double-level polysilicon layer allowed for layout of the NMOS memory cell in 266.5 µm2and design of the die in 34.3 mm2.