Hirotada Kuriyama

A 20 ns 4 Mb CMOS SRAM with hierarchical word decoding architecture

A 20-ns, 4-Mb CMOS SRAM with both 4 M*1 and 1M*4 organizations and fabricated using a quadruple-polysilicon, double-metal, twin-well 0.6- mu m CMOS process technology is described. A word-decoding architecture and a sensitive sense amplifier, combined with an address transition detector (ATD) technique, realize high-speed, low-power operation. Because conventional divided-word-line (DWL) structure cannot realize the high-speed and low-power word decoding in megabit SRAMs, hierarchical word decoding (HWD) is utilized. The RAM has a fast address mode using the 16-b parallel data bus scheme.<<ETX>>

Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM's

A lightly doped drain (LDD) structure was used in a gate-all-around TFT (GAT). This suppresses the leakage current much more than the LDD used in a single-gate TFT (SGT), and the current level of the GAT with the LDD is almost the same as that of the single-gate TFT (SGT) with the LDD keeping the GATs advantage of a high on-current. This is because the LDD effectively relaxes the electric field at the drain edge and reduces the effect of the electric field from the surrounded gate of the GAT. Furthermore, the GAT can suppress individual performance variations. The suppression mechanism of the individual performance variation in a GAT was investigated using a poly-Si TFT simulator. The thinner the channel poly-Si, the smaller the individual performance variation of the TFT. The GAT is more effective in decreasing the individual performance variation for thin channels than the SGT because the GAT can achieve the full depletion of the channel poly-Si with a channel thickness twice as large as the SGT. The GAT is eminently suitable for use in high-density, low-voltage operations, and low-power SRAMs.

Impact of a vertical /spl Phi/-shape transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond

We propose a Vertical /spl Phi/-shape Transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond. The V/spl Phi/T is a vertical MOSFET whose gate surrounds its channel region like a Greek alphabet /spl Phi/. It is built by penetration of the gate electrode (=word line) which has been formed beforehand. Application of the V/spl Phi/T for DRAM cell brings about cell size reduction to 50% and process simplification of about 10% at least. This is mainly because its bit line contact and the V/spl Phi/T are vertically aligned and storage node contact is eliminated. We have indicated that the V/spl Phi/T is an interesting candidate for the gigabit DRAM in view of size, cost and performance.<<ETX>>

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's

A single bitline cross-point cell activation (SCPA) architecture that reduces active power consumption and reduces the chip size of high-density SRAMs (static random access memories) is presented. The architecture enables the smallest column current possible without increasing the block division of the cell array. Since the decoder area is reduced due to less block division, the memory core can be smaller than with a conventional divided word line (DWL) structure. In the SCPA, the total active current is 15.9 mA, while in the conventional architecture it is 26.1 mA. In the SCPA, the memory cell size is equal to that in the conventional architecture; however, the number of local decoders is reduced from 64 to 8. Moreover, the number of GND lines is reduced because of a much smaller column current in SCPA. As a result, the area of the memory core is reduced by 10% in a 16-Mb SRAM. >

A C-switch cell for low-voltage and high-density SRAMs

We propose a novel static random access memory (SRAM) cell named complementary-switch (C-switch) cell. The proposed SRAM cell features: (1) C-switch in which an n-channel bulk transistor and a p-channel TFT are combined in parallel; (2) single-bit-line architecture; (3) gate-all-around TFT (GAT) with large ON-current of /spl mu/A order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-switch cell is built with only a triple poly-Si and one metal process using 0.3 /spl mu/m design rules.

A 0.4 μm Gate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories

We propose a novel thin-film-transistor (TFT) structure named gate-all-around TFT (GAT). Its fabrication process is very simple, in that we realize the gate-all-around structure using only a dummy nitride pattern. The GAT shows high channel conductance and features of shield structure peculiar to the double-gate structure. It can also eliminate an anomalous leakage current which appears in the sub-half-micron regime. Combining this process with sacrifice oxidation of the channel poly-Si, we obtained a GAT whose performance is nearly equal to that of single-crystalline metal-oxide-semiconductor field-effect transistors (MOSFETs). Since the GAT requires only one additional mask layer and no increase in TFT area as compared with the conventional single-gate TFT, it is suitable for a high-density and low-cost static-random-access-memory (SRAM). SRAM cells with this GAT have the potential to exhibit performance equivalent to that of the full-complimentary-MOS (CMOS) cell.

An analytical method of evaluating variation of the threshold voltage shift caused by the negative-bias temperature stress in poly-Si TFTs

The variation of the threshold voltage shift (V/sub th/ shift) caused by negative-bias temperature stress (-BT stress) in poly-crystalline silicon thin-film transistors (poly-Si TFTs) was investigated. Based on the chemical reaction caused by -BT stress at the poly-Si/SiO/sub 2/ interface and the poly-Si grain boundary, an analytical method of evaluating the variation of both the V/sub th/ shift and the initial V/sub th/ was proposed. It was shown from this analysis that the enlargement of the poly-Si grain, using Si/sub 2/H/sub 6/ gas could be a solution for efficient reduction of the easily hydrogenated dangling bonds which resulted in the V/sub th/ shift and suppression of the V/sub th/ shift and its variation. Moreover, it was suggested that there are two kinds of the dangling bonds; one is hydrogenated by hydrogenation and can be dehydrogenated by -BT stress; the other is not hydrogenated and the variation of its density is much smaller than the former.

An 8 ns 4 Mb serial access memory

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 mu m CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V. >

An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-/spl mu/m design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT.

A C-Switch cell for low-voltage operation and high-density SRAMs

We propose a novel single-bit-line SRAM cell called a Complementary-Switch (C-Switch) cell. This cell features a C-Switch which combines an n-channel bulk transistor and a p-channel TFT in parallel. Through the use of a single-bit-line architecture with the C-Switch and a high performance TFT called Gate-All-around TFT (GAT), the proposed cell achieves both stable operation at 1.5 V and a size reduction of 16% when compared to conventional structures. Moreover, we have realized this cell using only a triple poly-Si and one metal process on a 0.3 /spl mu/m design rule.