Shinpei Kayano

A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

This paper describes a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAMs. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K /spl times/ 8 full CMOS RAM has been developed with 2-/spl mu/m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six-transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in speed, the second poly-Si layer was replaced with a polycide (poly-Si + MoSi/SUB 2/) layer, thus providing a 50-ns address access time.

A 64Kb full CMOS RAM with divided word line structure

An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed.

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.

Output buffer with on-chip compensation circuit

An LV-CMOS output buffer with on-chip process and temperature variation compensation of the MOSFET is described. The compensation data acquisition circuit and output buffers are prepared in the I/O (input/output) buffer area of the half-micron CMOS ASIC (application-specific integrated circuit). The compensation circuit can control the channel width of the final stage MOSFET in the output buffer from 60% to 140% of typical process condition requirements with 13% resolution. By using the compensation circuit, the variation of propagation delay is within /spl plusmn/15% of the center value. In addition, di/dt at output signal switching is reduced. These features help ASIC users to design with timing-critical interchip communications and with high density packages.

A 45-ns 256K CMOS static RAM with a tri-level word line

A 32K words by 8-bit static RAM fabricated with a CMOS technology is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1.3-/spl mu/m design rule allowed layout of the NMOS memory cell in an area of 116.0 /spl mu/m/SUP 2/ and the die in 49.6 mm/SUP 2/.

A 4.5ns 256K CMOS SRAM with tri-level word line

A report on a CMOS SRAM with a peak current of 45mA obtained through the use of an address transition activated circuit combined with a tri-level word-line circuit will be presented.

A quasi-complementary-logic GaAs gate array employing air-bridge metallization technology

A GaAs logic circuit called QCL (quasi-complementary-logic) and a gate array employing air-bridge metallization are proposed. QCL has advantages over DCFL in delay, in power dissipation, and especially in function. Air-bridge metallization can cut 40% of the wiring delay. It is possible to design an array of more than 30 K gates using the process technology that is currently available.<<ETX>>

A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy

A 7-ns, 1 M&times;1/256 K&times;4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-&mu;m double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a supply voltage of -5.2 V. An access time of 7 ns has been obtained. Active 680 mW for &times;4 mode. The cell size is 5.4 &mu;m&times;7.2 &mu;m (38.88 &mu;m2); the die size is 5.46 mm&times;16.16 mm (88.24 mm2)

A fast 8K &#215; 8 mixed CMOS static RAM

This paper describes a fast 8K × 8 static RAM fabricated with a mixed CMOS technology. To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard bands around the wells. A 2-µm design rule combined with the double-level polysilicon layer allowed for layout of the NMOS memory cell in 266.5 µm2and design of the die in 34.3 mm2.

A novel memory cell for multiport RAM on 0.5 /spl mu/m CMOS Sea-of-Gates

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAMs with flexible bit-word configurations are available. Test chips containing seven generated RAMs were designed and fabricated on 0.5 /spl mu/m CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b/spl times/256w) is 4.8 ns at 3.3 V. >