Yoshiro Nakata

Evaluation technology of VLSI reliability using hot carrier luminescence

An evaluation technology for VLSI reliability using hot carrier luminescence has been developed. Problems with conventional electrical methods have been solved by the analysis of weak luminescence emitted from operating devices. Two applications are described. First, for the gate oxide evaluation, it is found that the best stress condition is determined by monitoring uniform photon count distribution emitted from the gate capacitors. Second, a method is proposed to find the weakest transistor in an LSI circuit against hot-carrier-induced degradation by counting photon emissions. This method is applied to the analysis of SRAMs (static RAMs) when the transistors to be improved have been detected. >

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t/sub RAS/=50 ns (typical) at V/sub cc/=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V/sub SS/ shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4- mu m CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM. >

Tunnel Structured Stacked Capacitor Cell (TSSC) with High Reliability for 64 Mbit dRAMs and Formation of Oxide-Nitride-Oxide Film (ONO) on 3-dimensionally (3d) Storage Electrode

We developed a new 3-dimensionally(3d) stacked capacitor structure, a tunnel structured stacked capacitor cell (TSSC), for 64Mbit dRAMs. The TSSC with 2 tunnels realized improved reliability the same as that of the conventional stacked capacitor (STC) and a capacitance of 29 fF with a capacitor height of 0.25 µm because of side-wall electrode formation. The equivalent thickness of SiO2 for the oxide nitride oxide (ONO) is 7.8 nm, and the cell area is 1.8 µm2. The uniformity of the ONO inside the tunnel of the TSSC was confirmed except for the corner of the tunnel, while the thickness of the ONO is slightly greater at the corner. At the corner, the top oxide film of the ONO is slightly thicker than that at the other areas, and accordingly, the shape of the plate electrode at the corner becomes round. These shape effects lead to no generation of the local field concentration at the corner inside the tunnel. They are applied to the other 3d stacked capacitors which have generally been proposed.