Shozo Okada

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t/sub RAS/=50 ns (typical) at V/sub cc/=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V/sub SS/ shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4- mu m CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM. >

A High Integrity and Low Resistance Ti-Polycide Gate Using a Nitrogen Ion-Implanted Buffer Layer

A new titanium-disilicide/polysilicon gate system using a nitrogen ion-implanted buffer layer which has high dielectric strength and low resistivity has been developed. The buffer layer of a nonstoichiometric silicon nitride layer approximately 30 nm-thick is formed with a N2+ dose below 5.0×1016 cm-2 at an acceleration energy of 15 keV. This layer can prevent intermixing of a titanium-disilicide film and a polysilicon film even after high-temperature annealing. Therefore, it can improve dielectric strength without increasing series resistances through those films.

Nucleation and growth mechanism of hemispherical grain polycrystalline silicon

The formation of the nucleus [Watanabe et al., Extended Abstracts of the 22nd Conference on Solid State Devices and Materials (1990), p. 873] is performed at low O2 partial pressure during annealing and the density of HSG nuclei increases as the annealing time becomes longer. HSGs grow upward from the amorphous silicon surface, and twin formations are generated in almost all the HSGs. For approximately 50% of whole HSGs, polycrystalline silicon grows downward from the bottom of the HSG. A common heterogeneous material both for the nucleus formation of HSG and for that of polycrystalline silicon growing downward is thought to be formed at the interface between HSG and polycrystalline silicon.

Tunnel Structured Stacked Capacitor Cell (TSSC) with High Reliability for 64 Mbit dRAMs and Formation of Oxide-Nitride-Oxide Film (ONO) on 3-dimensionally (3d) Storage Electrode

We developed a new 3-dimensionally(3d) stacked capacitor structure, a tunnel structured stacked capacitor cell (TSSC), for 64Mbit dRAMs. The TSSC with 2 tunnels realized improved reliability the same as that of the conventional stacked capacitor (STC) and a capacitance of 29 fF with a capacitor height of 0.25 µm because of side-wall electrode formation. The equivalent thickness of SiO2 for the oxide nitride oxide (ONO) is 7.8 nm, and the cell area is 1.8 µm2. The uniformity of the ONO inside the tunnel of the TSSC was confirmed except for the corner of the tunnel, while the thickness of the ONO is slightly greater at the corner. At the corner, the top oxide film of the ONO is slightly thicker than that at the other areas, and accordingly, the shape of the plate electrode at the corner becomes round. These shape effects lead to no generation of the local field concentration at the corner inside the tunnel. They are applied to the other 3d stacked capacitors which have generally been proposed.

ClF/sub 3/ gas compound for particle free contact hole etching

We propose a novel contact hole etching process using gas phase reaction of ClF/sub 3/. Particle free etching can be achieved by suppressing polymer deposition on the chamber wall while maintaining high oxide/silicon selectivity. ClF/sub 3/ can simultaneously etch oxide and clean the chamber wall. The same chamber can be used to remove the damaged silicon layer after contact hole formation and additional plasma apparatus, which has been necessary in conventional etching, is eliminated. This technology ensures high yield and cost-effective contact hole etching.<<ETX>>