You-Gang Chen

A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction

In this paper, a fast-locking all-digital deskew buffer with duty cycle correction is proposed and implemented. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With the aid of the three half delay lines technique, the mismatch between half delay lines causing the duty cycle distortion can be alleviated by interpolation. A balanced edge combiner to achieve a precise 50% output clock is also presented. A test chip is fabricated in 0.18-μm technology to demonstrate the feasibility of the proposed architecture. The circuit can accept the input clock rates from 250 to 625 MHz with the duty cycle variation within 30% and 70% to generate 50% output clocks. It preserves the capability of closed-loop control with a small area and power consumption.

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits

As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-mum CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a 7.00 times 10-5 bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide 8.84 times 10-3 BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 muW/MHz of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design .

A 0.18=μm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement

As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the injected noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. In this paper, we design and implement an 8-bit Markov random field carry lookahead adder (MRFCLA) probabilistic-based noise-tolerant circuit in 0.18μm CMOS process technology. This is the first working silicon design to prove the design concept of the noise-tolerant MRF circuits. The measurement results show that the proposed of the MRF adder can provide 28.7dB of noise-immunity as compared with its conventional CMOS design, when both circuits are facing the same server SNR environment. The MRF adder circuit can also achieve 10-6 BER when the supply voltage is only 0.45 V and SNR is only 10 dB.

A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. However, probabilistic-based designs cost larger hardware area. In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov random field carry lookahead adder (MRF_CLA), in 0.13 mum CMOS process technology. The measurement results show that the proposed MRF_CLA can provide 24.5 dB of noise-immunity enhancement as compared with its conventional CMOS design. Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design [1].

Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits

Along with the progress of advanced VLSI technology, noise issues in dynamic circuits have become an imperative design challenge. The twin-transistor design, is the current state-of-the-art design to enhance the noise immunity in dynamic CMOS circuits. To achieve the high noise-tolerant capability, in this paper, we propose a new isolated noise-tolerant (INT) technique which is a mechanism to isolate noise tolerant circuits from noise interference. Simulation results show that the proposed 8-bit INT Manchester adder can achieve 1.66times average noise threshold energy (ANTE) improvement. In addition, it can save 34% power delay product (PDP) in low signal-to-noise ratio (SNR) environments as compared with the 8-bit twin-transistor Manchester adder under TSMC 0.18-mu m process.

Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules

Data transmission on multiple clock domains faces reliable problems. The conventional globally asynchronous locally synchronous (GALS) technique can resolve the problem but has a high latency problem. In this paper, we present a novel asynchronous transmission technique called quasi-synchronous with an adaptive phase mechanism to reduce the transmission latency. Compared with the conventional GALS techniques, the proposed technique saves 50% ~ 83% of latency. It is implemented on standard-cell library by using TSMC 0.18 mum 1P6M CMOS technology

A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment

As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.

A high speed scalable shift-register based on-chip serial communication design for SoC applications

In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design (Kimura et al., 2003).

A fast and power-saving self-timed Manchester carry-bypass adder for Booth multiplier-accumulator design

In this paper, a fast and power-saving self-timed Manchester Carry-Bypass Adder (MCBA) is proposed based on the property analysis of the MCBA completion signal. By using a new self-timed approach, the critical path in the summation array of Multiplier-Accumulator (MAC) can be removed without conventional dual MCBA chain circuit. As a result, the speed of the proposed self-timed MCBA can be improved 23.3% and save 56.8% power consumption. Finally, a 16-bit 16-bit+40-bit Booth MAC with this new self-timed MCBA is demonstrated at 2.5V, 150MHz in UMC 0.25/spl mu/m process with 71.28mW power only.