Young-Kyun Jung

Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application

A novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell has been successfully developed, for the first time. The DC-SF cell consists of a surrounding floating gate with stacked dual control gate. With this structure, high coupling ratio, low voltage cell operation (program: 15V and erase: −11V), and wide P/E window (9.2V) can be obtained. Moreover, negligible FG-FG interference (12mV/V) is achieved due to the control gate shield effect. Then we propose 3D DC-SF NAND flash cell as the most promising candidate for 1Tb and beyond with stacked multi bit FG cell (2 ∼ 4bit/cell).

Limitation of WSix/WN Diffusion Barrier for Tungsten Dual Polymetal Gate Memory Devices

We compared WSix/WN and Ti/WN diffusion barriers for tungsten dual polymetal gate (W-DPG) application, in terms of device performance and gate oxide reliability. WSix/WN diffusion barrier shows degradation of gate oxide, which is found to be due to the B-N dielectric formation and subsequent breakdown of diffusion barrier. Relatively, Ti/WN diffusion barrier shows excellent device performance in terms of R/O delay and gate oxide reliability

Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B2H6-based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.