Hyeon-deok Lee

Low Dielectric Constant 3MS α-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process

The primary candidate for the barrier/etch stop layer in damascene process is silicon nitride. However, silicon nitride has a high dielectric constant. To reduce the effective dielectric constant in the copper damascene structure, silicon carbide, which is prepared by plasma enhanced chemical vapor deposition (PECVD) using 3 methyl silane source (Z3MS), is studied for the dielectric copper diffusion barrier. The dielectric constant of PECVD α-SiC:H is varied from 4.0 to 7.0 and the fourier transform infrared (FTIR) spectra peak intensity ratio of Si–CH3 bond to Si–C is also examined. The reduction in dielectric constant of α-SiC:H using 3MS gas seems to be related to the decreased density upon incorporation of Si–CH3 groups. The value of capacitance with α-SiC is 8–10% lower than that with PECVD SiN. The leakage current with α-SiC:H barrier is lower by 1 order of magnitude than that with PECVD SiN barrier.

Interfacial reaction in the poly-Si/Ta2O5/TiN capacitor system

For tantalum pentoxide capacitors in 1 Gbit dynamic random access memory, titanium nitride is adopted as the top electrode. After postannealing at temperatures higher than 750 °C, the capacitance of Ta2O5 reduces due to an interfacial reaction between TiN and Ta2O5. This was studied by high resolution electron microscopy and energy dispersive spectroscopy with a 1 nm electron probe. It is found that voids form along the interface between TiN and Ta2O5 and a large proportion of Ta dissolves into the TiN film. The origin of the reaction is concluded to be a large solid solubility of Ta in TiN. After Ta outdiffusion into TiN, vacancies agglomerate and form voids in Ta2O5 and thereby reduce its capacitance. Since the driving force of the reaction is the solid solubility of Ta in TiN, the amount of the reaction is affected by the thickness of the TiN films.

Microstructure analyses of the titanium films formed by the ionized sputtering process

Abstract We investigated the microstructure of the Ti-films formed on the (001) single crystal silicon wafers through the ionized sputtering process, and compared the results with those obtained by collimated sputtering. We found that the Ti-films created by ionized sputtering process without the substrate bias show less strong (002) textures than collimated sputtering. The Ti-films created by the ionized sputtering process with the substrate bias did not show any observable strong textures. We also found that the ionized sputtering processed Ti-films show about 4 nm thick amorphous Ti–Si interlayer, which is much thicker than that of the collimated sputtering process. The modifications of the microstructure of Ti-films are attributed to the ion bombardments during the ionized sputtering deposition process.

A New, Low-Thermal-Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured Hydrogen Silsesquioxane in Device

Employing an electron-beam (E-beam) cured hydrogen silsesquioxane (HSQ) based inorganic spin-on-glass as a pre-metal dielectric (PMD) material, we developed a simple planarization process with low thermal budget and good planarity in stacked capacitor dynamic random access memory (STC DRAM) device. We observe the basic E-beam cured HSQ film characteristics such as Fourier-transform infrared absorption spectra (FTIR), wet etch rate, film shrinkage, refractive index (RI), X-ray photoelectron spectroscopy (XPS), and electron spin resonance spectroscopy (ESR) in non-patterned wafer. No degradation of device characteristics such as Vth change, hot carrier hardness, and gate oxide quality has been observed. This process resulted in lower leakage current and higher capacitance for Ta2O5 capacitor as well as better planarization performance compared with the conventional undoped silicate glass (USG) etch back process. These results show that E-beam curing process as a low thermal budget PMD scheme would be a promising process for high capacitor dielectric materials.

Development and Optimization of Re-Oxidized Tunnel Oxide with Nitrogen Incorporation for the Flash Memory Applications

The reliability properties of NOR flash memory with 65nm node being developed in Samsung electronics are greatly improved by using the newly proposed re-oxidized tunnel oxide. Especially, by optimizing the process variables such as the re-oxidation thickness/time, the partial pressure of NO during annealing, and the kinds of re-oxidizing materials, the Vth shifts post cycling and after post-cycling bake were decreased to the level of 28% and 42% of conventional NO annealed tunnel oxide, respectively.

Effect of STI shape and tunneling oxide thinning on cell Vth variation in the flash memory

We studied factors which affect cell Vth variation in the floating gate flash memory. By simulation and experiment, we showed that the shape of STI (shallow trench isolation) and the tunnel oxide thickness in the STI edge were the main control factors. For example, sharp and thin oxide in the STI edge caused an uncontrolled F-N gate current in the program or erase operation, which directly indicated the amount of threshold voltage in the flash memory. Furthermore, we found that tunnel oxide thinning was closely related to the activation energy in the oxidation process. Smaller activation energy resulted in better thinning and better cell Vth distribution.

Enhanced exchange coupling constant and thermal stability of antiferromagnetically coupled media with thin Co interlayers

The magnetic properties and thermal stability of antiferromagnetically coupled (AFC) media with thin Co interlayers are investigated. Since the thermal stability is strongly dependent on the exchange coupling constant Jex in the AFC media, the thin Co interlayers were inserted on both interfaces of the Ru layer to obtain higher values of Jex. The Jex above 0.6 erg/cm2 was obtained in the AFC media with the Co interlayers above 1 nm in comparison with about 0.1 erg/cm2 in AFC media without the Co interlayers. The thermal stability of the AFC media with Co interlayers was greatly improved over those of the AFC media without Co interlayers.

Ge Implantation to Improve Crystallinity and Productivity for Solid Phase Epitaxy Prepared by Atomic Mass Unit Cross Contamination-Free Technique

Germanium (Ge) ion implantation was investigated for crystallinity enhancement during solid phase epitaxial (SPE) regrowth. Electron back-scatter diffraction (EBSD) measurement showed numerical increase of 19% of (100) signal, which might be due to the effect of pre-amorphization implantation (PAI) on silicon layer. On the other hand, electrical property such as off-leakage current of n-channel metal oxide semiconductor (NMOS) transistor degraded in specific regions of wafers. It was confirmed that arsenic (As) atoms were incorporated into channel area during Ge ion implantation. Since the equipment for Ge PAI was using several source gases such as BF3 and AsH3, atomic mass unit (AMU) contamination during PAI of Ge with AMU 74 caused the incorporation of As with AMU 75 which resided in arc-chamber and other parts of the equipment. It was effective to use Ge isotope of AMU 72 to suppress AMU contamination. It was effective to use enriched Ge source gas with AMU 72 in order to improve productivity.

Reduction of plasma-induced damage during intermetal dielectric deposition in high-density plasma

We have attempted to reduce the plasma-induced damage to the thin gate oxides during intermetal dielectric (IMD) gap-fill process by high-density plasma (HDP) chemical vapor deposition (CVD). It was revealed that the optimization of preheating step could reduce the damage. The H/sub 2/-based HDP CVD process was also effective in reducing plasma-induced damage compared with the conventional He-based process. The gate oxide failure was reduced remarkably at the low deposition temperatures less than 400/spl deg/C. Both the significant damage reduction and the excellent gap-fill performance were achieved by the adoption of the phosphorus silicate glass (PSG) using the low temperature H/sub 2/-based HDP CVD technique.

Electromigration reliability of dual damascene copper interconnect with different IMD structures

Electromigration behavior of dual damascene Cu interconnect has been investigated comparing PE-TEOS SiO/sub 2/ with fluorine doped SiO/sub 2/ (FSG). MTFs of FSG in both line and contact EM tests were significantly shorter than those of PE-TEOS. The higher compressive stress and fluorine of FSG dielectric are considered to affect the EM reliability performance of the confined Cu interconnect.