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Featured researches published by Young-Sub Yuk.


international solid-state circuits conference | 2012

A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting

Jong-Pil Im; Se-Won Wang; Kang-Ho Lee; Young-Jin Woo; Young-Sub Yuk; Tae-Hwang Kong; Sung-Wan Hong; Seung-Tak Ryu; Gyu-Hyeong Cho

This paper presents transformer-based self-starting boost converter architecture with low-power maximum power point tracking (MPPT) control for low-voltage thermoelectric generator applications. The minimum working voltage of the proposed boost converter is 40 mV with oscillation through a positive feedback loop formed by a native MOS and transformer. The oscillation autonomously starts up by thermal noise and VOUT is charged up to 1.2 V by the oscillation so that the control block can operate. After that, the transformer for start-up is reused as an inductor, and the normal boost converter mode is enabled for better energy transfer efficiency. An improved MPPT sensing method is also proposed to simplify the circuit. The prototype chip is implemented in a 0.13-μm CMOS process. It operates with an input voltage range of 40 mV to 300 mV and provides a maximum output power of 2.7 mW with a maximum efficiency of 61% at an output voltage of 2 V.


IEEE Transactions on Very Large Scale Integration Systems | 2014

PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator

Young-Sub Yuk; Seungchul Jung; Chul Kim; Hui-Dong Gwon; Sukhwan Choi; Gyu-Hyeong Cho

This paper presents a 65-nm CMOS low-dropout (LDO) regulator employing a super gain amplifier (SGA) and differential feed-forward noise cancellation to maximize the power supply rejection (PSR). The SGA in the error amplifier is augmented by a positive feedback current mirror, and this SGA boosts the loop gain through local negative feedback. With 1.2 V supply voltage, the LDO regulator has a 200 mV drop-out voltage and the ability to handle a maximum 25 mA load current. The measurement results show a -47 dB PSR ratio of up to 10 MHz and dc load regulation under 1 mV for full load current change.


european solid-state circuits conference | 2012

A CMOS LDO regulator with high PSR using Gain Boost-Up and Differential Feed Forward Noise Cancellation in 65nm process

Young-Sub Yuk; Seungchul Jung; Byunghun Lee; Se-Won Wang; Chul Kim; Gyu-Hyeong Cho

A 65nm CMOS Low Drop-Out (LDO) Regulator is presented employing Gain Boost-Up and Differential Feed Forward Noise Cancellation (DFFNC) to maximize the Power Supply Rejection. The gain boost-up consists of both negative feedback and positive feedback in the error amplifier. With a 1.2V supply voltage, this LDO regulator has a 200mV drop-out voltage and the ability to handle a maximum 25mA load current. The measurement results show a -47dB PSR ratio up to 10MHz and 0.8% of load regulation for the full load current change.


IEEE Transactions on Circuits and Systems | 2014

Auto-Scaling Overdrive Method Using Adaptive Charge Amplification for PRAM Write Performance Enhancement

Sukhwan Choi; Hyun-Sik Kim; Seungchul Jung; SiDuk Sung; Young-Sub Yuk; Hyuck-Sang Yim; Yoon-jae Shin; Junho Cheon; Changyong Ahn; Taekseung Kim; Yong-ki Kim; Gyu-Hyeong Cho

A PRAM write driver with an auto-scaling overdrive method is presented. The proposed overdrive method significantly reduces the rise time of the cell-current pulse for bit-line parasitic components of 3 pF and 6 k Ω, and it lowers the complexity of the overdrive control using an adaptive charge amplification technique. A rise time of less than 15 ns is achieved and shortened up to 4.7 times, and the total write-throughput is increased. The rise time is reduced consistently for all levels of the target-current by the auto-scaling effect. Therefore, cell heating control becomes more linear in program-and-verify (PNV) operation. Due to its simple adding-on structure, it is easily compatible with a conventional write driver. A prototype chip was implemented using a 0.18- μm CMOS process. It is also applicable to smaller-scale technology.


applied power electronics conference | 2011

Low-ripple hysteretic-controlled monolithic buck converter with adapted switching frequency for large step-down ratio applications

Se-Won Wang; Young-Jin Woo; Young-Sub Yuk; Byunghun Lee; Gyu-Ha Cho; Gyu-Hyeong Cho

20V maximum input voltage and 1A load current hysteretic control based monolithic buck converter with phase locked loop (PLL) is presented. To achieve advantage of hysteretic control and reduce inductor current ripple with ceramic output capacitor, hysteretic based control with PLL is adopted. Furthermore, in order to decrease inductor current ripple due to wide input voltage range, switching frequency is adapted to the input supply voltage. This buck converter is fabricated with 0.35 μm high voltage BiCMOS-DMOS (BCD) process.


symposium on vlsi circuits | 2010

High efficiency Single-Inductor Boost/Buck Inverting Flyback converter with hybrid energy transfer media and multi level gate driving for AM OLED panel

Se-Won Wang; Young-Jin Woo; Young-Sub Yuk; Gyu-Hyeong Cho; Gyu-Ha Cho

A hybrid-type Single Inductor Boost/Buck Inverting Flyback(SIBBIF) DC-DC Converter is presented. To increase the converter efficiency, a flying capacitor as well as an inductor is adopted as another energy transfer medium together with multi-level gate driver (MLGD). Besides, to enhance load transient response, hybrid fast transient control (HFTC) is adopted. The proposed chip is implemented in a 0.5-µm power BCD process and operates at 1.25 MHz with a max efficiency of 87.1% at an output power of 600 mW.


european solid-state circuits conference | 2010

Efficiency enhanced Single-Inductor Boost-Inverting Flyback converter with Dual Hybrid Energy transfer media and a Bifurcation Free Comparator

Se-Won Wang; Young-Jin Woo; Young-Sub Yuk; Byunghun Lee; Gyu-Hyeong Cho; Gyu-Ha Cho

A Dual Hybrid Energy transfer media (DHE) Single-Inductor Boost-Inverting Flyback (SIBIF) DC-DC Converter is presented. To increase the converter efficiency, two flying capacitors as well as an inductor are adopted as additional energy transfer media. Furthermore, in order to remove the bifurcation problem occurring in the SIMO type converter, a Bifurcation Free Comparator (BFC) is adopted. The proposed chip is implemented in a 0.5-μm power BCD process and operates at 1.25 MHz with a max efficiency of 89% at an output power of 600 mW.


power electronics specialists conference | 2008

Hybrid switching amplifier using a novel two-quadrant wideband buffer for dynamic power supply applications

Tae-Woo Kwak; Min-Chul Lee; Young-Sub Yuk; Kang-Ho Lee; Hyun-Hee Park; Chul Kim; Gyu-Hyeong Cho

A hybrid switching amplifier for dynamic power supply applications is presented. To achieve both high speed and high efficiency, a wideband buffered linear amplifier is combined with a hysteretic controlled switching amplifier. To obtain high linearity and reduce switching loss at low power levels where the switching amplifier is not needed, the linear amplifier supplies all load current with the switching one disabled. The novel two-quadrant linear amplifier as a voltage source for regulating the output voltage has very low output impedance of about 200 m Omega around the switching frequency, a high current-driving capability of maximum 220 mA and a bandwidth wider than 7 MHz. The hybrid amplifier can drive a circuit with an equivalent impedance of 7 Omega and supply a maximum output power of 1.1 W with a maximum efficiency of about 91%. Its output voltage ranges from 0.3 V to 2.9 V for a 3.3V supply. The chip is fabricated using only thick-oxide devices in a 0.13 um CMOS process and occupies an area of 3.9 mm2.


SID Symposium Digest of Technical Papers | 2010

60.2: Low-Power Consumptive Luminance Compensation for a Digital Driving AMOLED Display using a Multiple Output Boost Converter

Se-Won Wang; Hanh-Phuc Le; Young-Jin Woo; Young-Sub Yuk; Jin‐Hun; Tae-Hwang Kong; Jong-Pil Im; Byung‐Sang Jung; Jun-Han Choi; Sung-Wan Hong; Gyu-Hyeong Cho; Ho‐Min Lim; Gyu-Ha Cho; Sung-il Kim

The luminance of AMOLED displays varies depending on the temperature owing to panel degradation. In this paper, a luminance compensation method using a monitor pixel with a multiple output boost converter and DAC for digital driving scheme is introduced. This method makes the panel luminance constant irrespective of the temperature. Furthermore, it has lower power consumption compared with the previous compensation method using monitor pixel.


international solid-state circuits conference | 2010

A 105dB-gain 500MHz-bandwidth 0.1Ω-output-impedance amplifier for an amplitude modulator in 65nm CMOS

Chul Kim; Chang-Seok Chae; Young-Sub Yuk; Yi-Gyeong Kim; Jong-Kee Kwon; Gyu-Hyeong Cho

Polar modulation, where a constant-amplitude phase signal is amplified by an efficient switched-mode power amplifier (PA) and an envelope signal is modulated at the drain of the PA, has been proven to improve efficiency and linearity of the PA system. However, the amplitude modulator (AM) used in such modulation systems must have wide bandwidth, low switching ripple and high efficiency. Although several AM structures have been reported the hybrid switching amplitude modulator (HSAM) shows excellent performance [1–3]. The HSAM consists of a linear amplifier as a voltage source and a switching amplifier as a dependant current source. The linear amplifier using voltage feedback defines output voltage with high frequency information in a bandwidth-expanded envelope signal and the switching amplifier using current feedback drives almost all the current to develop output voltage with the help of a current sensing circuit. If the current sensing circuit does not work well, it makes an offset to the switching amplifier and results in additional power consumption of the linear amplifier [2]. To meet a stringent spectral mask, low output impedance of the linear amplifier is needed [1]. In conclusion, wide bandwidth and low output impedance of the linear amplifier, and accurate current sensing are critical points in the design of the HSAM.

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