YoungChai Jung

Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge

We measured and analyzed the subthreshold degradation of the gate-all-around (GAA) silicon nanowire field-effect transistors with the length of 300/500 nm and the radius of 5 nm. An analytical model incorporating the effect of interface traps quantitatively explained the measured subthreshold swing (SS) degradation. A simple electrostatic argument showed that the GAA device had smaller degradation of SS values than planar devices for the same interface trap densities.

Electrical Characteristics of the Backgated Bottom-Up Silicon Nanowire FETs

We report the electrical characteristics of backgated silicon nanowire (SiNW) FETs at temperatures ranging from 300 to 160 K. The voltage drop along the intrinsic part of the silicon nanowire (SiNW) was obtained by modeling the source/drain contacts as Schottky diodes. The field effect mobility values obtained from the extracted intrinsic voltage drop showed activation behaviors in the given temperature range. The activation energy was smaller than that of previously reported Ge nanowires.

Observation of gate bias dependent interface coupling in thin silicon-on-insulator metal-oxide-semiconductor field-effect transistors

We fabricated and characterized a silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor with a SOI film thickness of 26nm. The measured data at room temperature showed that the transconductance peak in the front gate bias shifted and then split into two peaks as the back gate voltage (VBS) decreased. The VBS regime of this splitting was opposite to that of thick SOI devices, suggesting a different physical mechanism in our thin device. Our device also showed VBS dependences of the threshold voltage and the subthreshold swing, which were different from those of thick SOI devices. Our data were explained by the volume inversion of a thin SOI in which both front and back gates strongly modulated the conduction band and charge state of the SOI. The splitting was interpreted as due to the population of the second subband of a triangular quantum well.

Electrical characteristics of the back-gated bottom-up silicon nanowire field effect transistor

We report electrical characteristics of back-gated silicon nanowire field effect transistors (SNWFETs) fabricated using silicon nanowires synthesized by a standard vapor-liquid-solid process. It is shown that the mobilities obtained from the measured transconductances are reasonable only when the nanowire is fully depleted.

Fabrication of poly-silicon nano-wire transistors on plastic substrates.

We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150 degrees with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.