Che-Wei Chou

Yield-enhancement techniques for 3D random access memories

Three-dimensional (3D) integration technology using through silicon via (TSV) is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for using the 3D integration technology. Introducing redundancies into a large-capacity RAM in design phase is essential for yield improvement. In this paper, we present yield-enhancement techniques for 3D RAMs. In addition to typical redundancy schemes are used to improve the yield of 3D RAMs, an inter-die redundancy scheme is proposed. Also, a stacking flow is proposed to further improve the final yield of 3D RAMs with the proposed inter-die redundancy scheme.

A Test Integration Methodology for 3D Integrated Circuits

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC’99 b19 benchmark is only about 0.15%.

Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

Three-dimensional (3D) integration is expected to cope with the difficulties faced by current 2D system-on-chip designs using through silicon via (TSV). However, coupling capacitance exists between two neighboring TSVs such that TSVs are prone to crosstalk faults. In this paper, we propose a builtin self-test (BIST) scheme for the post-bond test of TSVs with crosstalk faults in 3D ICs. A test algorithm for testing crosstalk faults of TSVs is proposed. The proposed BIST scheme has the feature of low area cost. Simulation results show that the area overhead of the BIST circuit implemented with 90nm CMOS technology for a 512×16 TSV array in which each TSV cell size is 15 × 15μm2 is 6.7%.

A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy

3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.

Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs

Built-in self-repair (BISR) is one promising approach for improving the yield of memory cores in an system-on-chip (SOC). This paper presents a test scheduling approach for BISR memory cores under the constraint of maximum power consumption. An efficient test scheduling algorithm based on the early-abort probability is proposed. Experimental results show that the scheduled results of the proposed algorithm have lower expected test time in comparison with the previous work. For ITC’02 benchmarks, for example, about 10.7% average reduction ratio of expected test time can be achieved by the proposed algorithm.

A built-in self-test scheme for 3D RAMs

Three-dimensional (3D) random access memory (RAM) using through-silicon vias for inter-die interconnects has been considered as a new approach to overcome the memory wall. In this paper, we propose a built-in self-test (BIST) scheme for 3D RAMs. In the BIST scheme, a clock-domain-crossing-aware test pattern generator is proposed to cope with the clock-domain-crossing issue. An inter-die synchronization mechanism is also proposed to synchronize the BIST circuits in different dies. Furthermore, the BIST circuit provides the high-programmability feature to support the selection of RAMs in a die for testing such that it can support thermal management during the test. We design the proposed BIST scheme in a 3D IC with processor and RAM dies. Experimental results show that the area cost of the BIST circuit is very small. The area overhead of the BIST circuit for four 8192×64-bit RAMs in a die is only 0.45% using TSMC 90nm 1P9M CMOS process technology.

A low-cost built-in self-test scheme for an array of memories

Modern processor and computation-intensive chips typically use the design style of multi-core chip architecture with identical logic and memory cores. Although memory built-in self-test (BIST) is a mature technique for testing embedded memories, testing multiple small memories using small area cost is still a challenge. This paper proposes a low area-cost BIST scheme for an array of memories and interconnections between memory cores and logic cores. To reduce the area cost without incurring long testing time, the BIST scheme tests multiple identical memories in a pipeline and each memory with a serial test interface. Experimental results show that the proposed BIST scheme has small area cost. For example, the proposed BIST scheme for 16 1024×64-bit RAMs only needs about 0.89% hardware overhead.

A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs

Three-dimensional (3-D) integration technology using through-silicon via (TSV) is an emerging integrated-circuit (IC) design technology. In this paper, we propose a repair scheme to enhance the yield of TSVs in 3-D ICs. The proposed TSV repair scheme uses an enhanced test access architecture to alleviate the requirement of additional repair registers such that the area cost can be drastically reduced. In comparison with existing scan-based test and repair approaches, simulation and analysis results show that the proposed TSV repair scheme can provide the best final yield and consume the smallest area cost for 128 TSVs with one spare TSV. On the other hand, the proposed repair schemes with 1149.1-based and 1500-based wrapper cells for 128 TSVs only need 12% and 20% additional area cost in comparison with the 1149.1 and 1500 test access architectures.

Hierarchical Test Integration Methodology for 3-D ICs

In this paper, we propose a hierarchical test integration method for 3-D ICs. The method can handle a die with logic cores and memory cores. In addition to handle the test controlling of a hierarchical 3-D IC, furthermore, it also can support the test controlling of a 3-D IC with multiple towers. For a 3-D IC, the hierarchical test integration method uses two types of 1149.1-based test interfaces for the bottom die and nonbottom dies. Therefore, the test access ports for the two test interfaces are the same. Also, the number of required test pads of the proposed test interface is only 4. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing.

Built-in self-diagnosis and test time reduction techniques for NAND flash memories

This paper presents a low-cost built-in self-diagnosis (BISD) scheme for NAND flash memories, which can support the March-like test algorithms with page-oriented data backgrounds. Two simple test time reduction techniques are also proposed to reduce the test time. Experimental results show that the proposed BISD circuit for a 2M-bit flash memory only needs 1.7K gates. Also, the proposed test time reduction techniques can effectively reduce the test time. Analysis results show that they can reduce the test time to 48.628% of the normal test scheme for a 4G-bit flash memory tested by the March-FT test algorithm with solid data backgrounds.