Yuan-Hua Chu

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical VDD to 350 mV ( ~ 100 mV lower than the threshold voltage) with VDDMIN limited by Read operation. Data can be written successfully for VDD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 μW at 350 mV, 25 °C.

Feedback-controlled split-path CMOS buffer

New CMOS buffers, called feedback-controlled split-path (FS) CMOS buffers, are proposed and analyzed. By using the control of the output feedback signal, the short-circuit current of the output stage can be eliminated. The pull-high and pull-down driving paths of the output stage are split and they can be sized individually to acquire lower delay time, smaller area, and lower power dissipation. A general method is also proposed to further eliminate the short-circuit current in each stage of the FS buffer and to reduce the area, power dissipation, and delay time. High-speed buffers operated at 200 MHz are designed with 0.5ns rise/fall time and 2.5 nF output load. Simulation results show that the power-delay product of the FS buffers with two split-paths and four split-paths are only 59% and 47% that of the conventional fixed-taper buffer, respectively.

PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems

On-chip regulators are becoming increasingly important for ultra-low voltage nano-scale SoC systems. In this paper, an all-digital controlled linear regulator is presented. A novel Process-Voltage-Temperature (PVT) -aware design is implemented to mitigate environmental variations and to guarantee the resolution of the liner regulator. The proposed digital voltage regulator can achieve up to 98.4% current efficiency. This design leads to three major advantages: (1) fast response time of 60ns, (2) low quiescent current 162μA in a stable state, and (3) PVT tolerance. The settling time is about 138ns. The output voltage error in 0.3V stable states with error improvement of the resolution using PVT-aware DED is around 50%. The best FOM at the regulated voltage (VREG) of 0.51V is 4.2 pA·s. This digital controlled voltage regulator is designed and implemented for near-/sub- threshold operations. It can generate VREG from 0.3V ~ 0.51V in steps of 30mV without resolution degradation under PVT variations. The total area of the regulator is about 388.6×35.7μm2 using TSMC 65-nm low-power bulk CMOS technology.

Unbalanced current latch sense amplifier for low-power high-speed PLDs

This paper describes an unbalanced current latch sense amplifier (UCLSA) for low-power high-speed programmable logic device (PLD) design. With one side of the differential inputs of the UCLSA connected to the bit line and the other to a fixed bias, the UCLSA amplifies the small voltage difference generated in the single-ended bit line of the PLD. A pair of differential signals are generated and the sense current is stopped automatically. The UCLSA can amplify an input voltage swing on the bit line as small as 20 mV. Low-power and high-speed performances can be achieved by using the UCLSA.

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction

In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best (lowest) FOM of 0.76 pA·s can be realized.

An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications

A 1V~1.2V battery input, 0.4V~0.6V output low-power all-digital power management unit (PMU) composed of a high-efficiency digital buck converter (DBC) and a fast-transient digital low drop-out (DLDO) regulator is developed for energy-efficient SoC applications. A fully integrated 2-to-1 switched-capacitor dc-dc converter is combined together to reduce the quiescent current of digital control circuits. The digital pulse width modulation (DPWM) with clock frequency gating further reduces the power consumption of buck converter in steady state. From experiment results, the peak power efficiency of the proposed buck converter is 90% with an output power range of 30μW to 3mW and the peak current efficiency of DLDO is 98.8% at 5mW. Moreover, the proposed DLDO achieves 92ns/130ns transition time in 60mV voltage step to dynamically scaling the voltage of supply voltage in digital circuits. This chip is designed and fabricated in 65nm CMOS process for verification.

Multiple output switched capacitor DC-DC converter with capacitor sharing for sensor-fusion platforms

In this paper, a multiple output switched capacitor (SC) DC-DC converter with capacitor sharing technique is proposed for event-driven energy-efficient sensor-fusion platforms. The converter is able to convert 1.2V supply voltage to five different output voltages ranging from 0.44V to 2.2V to power different building blocks in the system. A part of the flying capacitor can be shared between five SC cells according to the loading condition to reduce the chip area. With capacitor sharing concept, 36% of on-chip metal-insulator-metal (MIM) capacitor can be reduced. The proposed switched capacitor DC-DC converter is implemented by TSMC 90nm CMOS process. The simulation results show the converter achieves 80% maximum conversion efficiency with less than 20mV output ripple.

A radio-controlled receiver for clocks/watches and alarm applications

This paper presents a radio-controlled clock/alarm (RCC) receiver. The proposed RCC receiver adopts a signal transmitted technique via amplitude modulation (AM) principle. This I/Q DPS adopts a multi-phase sampled technique using a multi-phase ring oscillator. The decoding circuit can amplify the input signal and filter the noise signal to achieve high quality signal source. The low noise amplifier (LNA) circuit can receive the smaller input power. The operational frequency of all-digital clock generator (ADCG) is programmable for the broadcast frequency of local communication systems, such as the DCF77 (Germany), WWVB (US), JJY (Japan), BPC (CN), and MSF (UK). The digital loop filter of ADCG adopts a successive-approximation register (SAR) algorithm for fast locking time. This RCC receiver is implemented in a 0.18 um CMOS process and the core area of RCC receiver is 1152 × 1572 μm2. The accuracies of operational frequencies of ADCG are less than ±264 ppm for all radio broadcasting frequencies. The voltage gain of LNA is 24.44 dB to achieve the lower input power. The measured environment of clock/alarm application is set and verified for the test chip of RCC receiver.

An ultra-low voltage hearing aid chip using variable-latency design technique

This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)

In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.