Yuan-Sheng Lin

High density metal-insulator-metal capacitor based on ZrO2∕Al2O3∕ZrO2 laminate dielectric

The metal-insulator-metal (MIM) capacitor for analog and rf applications has been developed with ZrO2∕Al2O3∕ZrO2 laminate as the dielectric. The high capacitance density of 21.54fF∕μm2 can be achieved due to the tetragonal ZrO2 which makes the higher dielectric constant of 38.7. This MIM capacitor also demonstrates the quadratic voltage coefficient of 2443ppm∕V2 and the good leakage current of 2.11×10−6A∕cm2 at 2V which is ascribed to the inserted Al2O3. Since the Schottky emission is suggested as the major dielectric conduction mechanism, a further reduced quadratic voltage coefficient and leakage characteristic can be realized by using a high work-function electrode. The combination of the promising electrical properties and the desirable process integration renders this structure highly suitable for advanced MIM capacitors.

Nitrided Tetragonal

Employment of a tetragonal ZrO2 film as the charge-trapping layer for nonvolatile memory was investigated and the NH3 nitridation effect of the ZrO2 film on memory performance was also explored in this letter. The permittivity of the tetragonal ZrO2 film is slightly reduced from 38.7 to 36.9 after nitridation; nevertheless, nitridation introduces more trapping sites and passivates the grain boundary channel which results in a high operation speed in terms of 2.6-V flatband voltage shift by programming at +10 V for 10 ms and a good retention characteristic with 20.2% charge loss after ten-year operation at 125degC, both are superior to that without NH3 nitridation. Most importantly, the process is fully compatible with existent ULSI technology and paves the way to adopt a high-permittivity crystalline dielectric as the charge-trapping layer for future high-performance nonvolatile memory.

\hbox{ZrO}_{2}

With a Si substrate, the p-MOSFET formed on a thin Ge layer with the thermal SiON as the gate dielectric was electrically characterized in this letter. The desirable passivation of the Ge channel is evidenced by the interface trap density lower than 3.46 times1011 cm-2middoteV-1. A 1.74 times higher peak hole mobility than that of the Si universal one is obtained by the Ge MOSFET due to the low interface trap density and the good Ge crystallinity. With the source/drain region mainly formed on the Si substrate, the Ge MOSFET also demonstrates the excellent junction leakage. Combining these promising electrical characteristics, the thermal SiON with the device structure holds the potential to be applied to high-performance Ge MOSFETs.

as the Charge-Trapping Layer for Nonvolatile Memory Application

With Si substrate, the silicon-oxide-nitride-oxide-silicon-type nonvolatile memory formed on a Ge layer with thermal SiO 2 as the tunnel dielectric is explored in this work. The promising performance of the Ge-based memory is evidenced by the large hysteresis memory window, the high operation speed of 4.2 V flatband voltage shift by erasing at -16 V for 1 ms, the negligible memory window degradation up to 10 5 operation cycles, and a good retention characteristic with 15% charge loss after a 10 year operation. The asymmetry in programming and erasing speed is observed, and the mechanism, along with the approaches to alleviate this henomenon, is also discussed. Most importantly, the Ge-based memory device can be implemented by the process fully compatible with existent ultralarge-scale integration technology, paving the way to enable high performance nonvolatile memory for the next-generation electronic system.

Electrical Characteristics of Thermal-SiON-Gated Ge p-MOSFET Formed on Si Substrate

Si nanocrystal with a high density of 5.1 X 10 11 cm -2 and an average size of 7.2 nm has been achieved on the NH 3 -nitrided tunnel oxide, and the density is higher than that formed on the untreated tunnel oxide by a factor of 3.2. The higher density obtained by this technique is attributed to the lower activation energy for the Si nanocrystal nucleation growth on the nitrogen-containing surface of the nitrided tunnel oxide. The memory device with such a high nanocrystal density demonstrates a 1.79 V threshold voltage shift by programming at 10 V for 10 ms and a negligible memory window degradation up to 10 6 program/erase cycles. The good charge storage capability is evidenced by an extrapolated 10 year memory window of 0.92 V at 150°C.

Ge-Based Silicon–Oxide–Nitride–Oxide–Silicon-Type Nonvolatile Memory Formed on Si Substrate

In this letter, TiN nanocrystals three-dimensionally embedded in the Si3N4 formed by spinodal phase segregation was investigated as the discrete charge-trapping layer in a metal-oxide-nitride-oxide-silicon structure for nonvolatile-memory applications. TiN-nanocrystal formation was verified by X-ray diffraction analysis while the 3-D distribution of nanocrystals in the Si3N4 film was confirmed by transmission electron microscopy with the average size of 5.1 nm and a density of 9.8 × 1011cm-2. The promising memory performance was evidenced by the large memory window of 1.81 V with plusmn4-V program/erase voltage, the high operation speed of 1.52-V threshold-voltage shift by programming at +4 V for 10 ms, the negligible memory-window degradation up to 105 operation cycles, and 11% charge loss after ten-year operation. Most importantly, the charge-storage structure can be formed by a cosputtering approach which is simple and fully compatible with existent ultralarge scale integration technology.

High-Density Silicon Nanocrystal Formed on Nitrided Tunnel Oxide for Nonvolatile Memory Application

The thermal SiO2 gated Ge metal-oxide-semiconductor (MOS) capacitor on Si substrate was accomplished by the direct oxidation of the amorphous Ge layer and a subsequent forming gas annealing. The epitaxial Ge on Si substrate shows the good crystallinity and the smooth interface with the thermal oxide. The oxide on the Ge layer is confirmed to have SiO2 bonding structure with tiny Ge content. The negligible hysteresis and the small frequency dispersion in C-V characteristics indicate the desirable oxide quality. The conduction mechanism through the oxide has been verified as Fowler–Nordheim tunneling with the conduction band offset of 2.81eV. Another intriguing point of this process lies in the fact that it provides a simpler and ultralarge scale integration-compatible approach to fabricate high-performance Ge MOS field effect transistors as compared with previous works.

Nonvolatile Memory With TiN Nanocrystals Three-Dimensionally Embedded in

Hybrid nonvolatile memory with Si nanocrystals embedded in the Si<inf>3</inf>N<inf>4</inf> has demonstrated higher operation speed than a plain silicon-oxide-nitride-oxide-silicon (SONOS) memory while maintaining better retention characteristic than a pure Si nanocrystal memory [1]. Based on this concept, TiN nanocrystals embedded in the Al<inf>2</inf>O<inf>3</inf> have exhibited improved memory characteristics [2]. Because Si<inf>3</inf>N<inf>4</inf> has been verified to possess more trapping sites than Al<inf>2</inf>O<inf>3</inf>, TiN nanocrystals three-dimensionally embedded in the Si<inf>3</inf>N<inf>4</inf> film was studied in this work as the charge trapping layer. In fact, three-dimensionally incorporating metal nanocrystals in the Si<inf>3</inf>N<inf>4</inf> (double heterogeneous stack) has been previously investigated and presented better memory performance than that with single heterogeneous stack [3]. However, the formation of this double heterogeneous floating-gate requires sequential deposition of Si<inf>3</inf>N<inf>4</inf> and metal nanocrystals which is relatively complicated and necessitates rigorous process parameter control. To address this issue, a single co-sputtering process was explored to achieve the hybrid memory structure by spinodal phase segregation.