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Dive into the research topics where Lun-Lun Chen is active.

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Featured researches published by Lun-Lun Chen.


IEEE Electron Device Letters | 2009

Nitrided Tetragonal

Yung-Hsien Wu; Lun-Lun Chen; Yuan-Sheng Lin; Ming-Yen Li; Hsiao-Che Wu

Employment of a tetragonal ZrO2 film as the charge-trapping layer for nonvolatile memory was investigated and the NH3 nitridation effect of the ZrO2 film on memory performance was also explored in this letter. The permittivity of the tetragonal ZrO2 film is slightly reduced from 38.7 to 36.9 after nitridation; nevertheless, nitridation introduces more trapping sites and passivates the grain boundary channel which results in a high operation speed in terms of 2.6-V flatband voltage shift by programming at +10 V for 10 ms and a good retention characteristic with 20.2% charge loss after ten-year operation at 125degC, both are superior to that without NH3 nitridation. Most importantly, the process is fully compatible with existent ULSI technology and paves the way to adopt a high-permittivity crystalline dielectric as the charge-trapping layer for future high-performance nonvolatile memory.


Applied Physics Letters | 2011

\hbox{ZrO}_{2}

Yung-Hsien Wu; Chia-Chun Lin; Lun-Lun Chen; Yao-Chung Hu; Jia-Rong Wu; Min-Lin Wu

A Ge-stabilized tetragonal ZrO2 dielectric with a permittivity (κ) value of 36.5 has been obtained by annealing a ZrO2/Ge/ZrO2 laminate at 500u2009°C and it is a more reliable approach toward stabilizing a tetragonal ZrO2 film. However, metal-insulator-metal (MIM) capacitors with the sole tetragonal ZrO2 film as an insulator achieve a high capacitance density of 27.8u2002fF/μm2 at the price of a degraded quadratic voltage coefficient of capacitance (VCC) of 81u2009129u2002ppm/V2 and unacceptably high leakage current. By capping an amorphous La-doped ZrO2 layer with a κ value of 26.3 to block grain boundaries-induced leakage paths of the crystalline ZrO2 dielectric, high-performance MIM capacitors in terms of a capacitance density of 19.8u2002fF/μm2, a VCC of 3135u2002ppm/V2, leakage current of 6.5×10−8u2002A/cm2 at −1 V, as well as a satisfactory capacitance change of 1.21% after ten-year operation can be realized.


Applied Physics Letters | 2011

as the Charge-Trapping Layer for Nonvolatile Memory Application

Jia-Rong Wu; Yung-Hsien Wu; Chin-Yao Hou; Min-Lin Wu; Chia-Chun Lin; Lun-Lun Chen

CF4 plasma treatment on germanium (Ge) surface is proposed in this work to alleviate the strong Fermi level pinning between metal/Ge, and its effectiveness is also explored for n- and p-type Ge wafers. It is found that samples with CF4 plasma treatment reveal conduction behavior transition between Schottky and ohmic characteristics, a metal-work-function-dependent Schottky barrier height as well as modulated contact resistance, and these results confirm the depinning of Fermi level. This depinning can be explained by the effective capability in passivating dangling bonds at Ge surface through fluorine atoms and the formation of Ge-F binding with partial ionic property, both of which are helpful in decreasing the number of surface states and consequently release the pinning effect.


Applied Physics Letters | 2010

High-performance metal-insulator-metal capacitor with Ge-stabilized tetragonal ZrO2/amorphous La-doped ZrO2 dielectric

Yung-Hsien Wu; Min-Lin Wu; Jia-Rong Wu; Lun-Lun Chen

A Ge-stabilized tetragonal ZrO2 (t-ZrO2) film formed by incorporating Ge atoms thermally driven from an underlying Ge layer into a ZrO2 film was investigated as the gate dielectric for Ge metal-oxide-semiconductor (MOS) capacitors fabricated on a Si substrate. A sole t-ZrO2 film on Ge is not eligible for the gate dielectric because of the poor interface quality. By using a thermally-grown ultrathin GeO2 film as an interfacial layer, the t-ZrO2/GeO2/Ge stack shows improved interface characteristics and a permittivity (κ) value of 36.6 for the t-ZrO2. In addition, the stack also demonstrates good leakage current since the amorphous GeO2 layer terminates grain boundary channels in the crystalline ZrO2. Further leakage current suppression can be achieved by a H2 annealing of the t-ZrO2/GeO2/Ge stack since the defects at grain boundaries can be effectively passivated, which makes a leakage current of 1.08×10−6u2002A/cm2 at VFB−1u2002V for effective oxide thickness of 1.66 nm and paves an alternative avenue to develop ...


IEEE Electron Device Letters | 2010

Impact of fluorine treatment on Fermi level depinning for metal/germanium Schottky junctions

Yung-Hsien Wu; Lun-Lun Chen; Jia-Rong Wu; Min-Lin Wu; Chia-Chun Lin; Chia-Hsuan Chang

A cubic ZrO2 film formed by annealing of amorphous ZrON has been investigated as the charge-trapping layer for nonvolatile memory. The memory with a nitrogen-stabilized cubic ZrO2 film shows promising performance in terms of 3.81-V hysteresis memory window by ± 7-V program/erase voltage and 1.98-V flatband-voltage shift by programming at +7 V for 10 ms. As compared to that with an amorphous ZrON film, the improved performance is due to the greatly enhanced κ-value of 32.8 and the increased trapping sites provided by grain boundaries. Additionally, it shows 28.6% charge loss after ten-year operation at 85°C. Although it is worse than that with an amorphous ZrON film, it is advantageous over an atomic-layer-depositiongrown tetragonal ZrO2 film in terms of reduced leakage current. Improved retention can be accomplished by passivation of grain boundaries and/or high- κ double quantum barrier as the tunnel and blocking dielectric.


IEEE Electron Device Letters | 2010

Ge-stabilized tetragonal ZrO2 as gate dielectric for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate

Yung-Hsien Wu; Lun-Lun Chen; Rong-Jhe Lyu; Ming-Yen Li; Hsiao-Che Wu

Abstract-The combination of tetragonal ZrO<sub>2</sub> (t-ZrO<sub>2</sub>) and amorphous Al<sub>2</sub>O<sub>3</sub> was explored as the gate dielectric for Si-based MOS devices. Because of the absence of a ZrSiO<sub>4</sub> and/or ZrSi interfacial layer, the thermally stable t-ZrO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>/Si stack is more eligible than the Al<sub>2</sub>O<sub>3</sub>/t-ZrO<sub>2</sub>/Si stack for the gate dielectric since it demonstrates larger capacitance, smaller hysteresis, better frequency dispersion, lower leakage current, and more robust reliability. By employing additional NH<sub>3</sub> plasma nitridation to well passivate the grain boundaries of the t-ZrO<sub>2</sub> film, without compromising its κ-value, a greatly reduced leakage current of 2.9 × 10<sup>-8</sup> A/cm<sup>2</sup> can be achieved at gate bias of flatband voltage (V<sub>fb</sub>)-1 V with an effective oxide thickness of 1.64 nm, which paves a new way to develop a high-performance crystalline gate dielectric for advanced MOS devices.


Applied Physics Letters | 2011

Nonvolatile Memory With Nitrogen-Stabilized Cubic-Phase

Yung-Hsien Wu; Min-Lin Wu; Rong-Jhe Lyu; Jia-Rong Wu; Lun-Lun Chen; Chia-Chun Lin

By adopting an amorphous Y2O3 passivation layer, which provides a wide band gap and well passivates Ge surface without the presence of GeOx, a high-permittivity (κ) crystalline ZrO2/Y2O3 stack was explored as the gate dielectric for Ge metal-oxide-semiconductor (MOS) devices on Si substrate. The crystalline ZrO2 is a Ge stabilized tetragonal/cubic dielectric with the κ value of 36.1 and was formed by depositing a ZrO2/Ge/ZrO2 laminate and a subsequent 500u2009°C annealing. The high-κ crystalline ZrO2/Y2O3 gate stack shows promising electrical characteristics in terms of low interface trap density of 5.8×1011u2002cm−2u2009eV−1, negligible hysteresis, and leakage current of 5.6×10−4u2002A/cm2 at gate bias of flatband voltage (VFB) 1 V for equivalent oxide thickness of 1.13 nm. This gate stack not only demonstrates the eligibility for advanced Ge MOS devices but introduces a more reliable process to form a high-κ crystalline gate dielectric.


IEEE Electron Device Letters | 2012

\hbox{ZrO}_{2}

Yung-Hsien Wu; Wei-Yuan Ou; Chia-Chun Lin; Jia-Rong Wu; Min-Lin Wu; Lun-Lun Chen

Metal-insulator-metal (MIM) capacitors with crystalline-TiO<sub>2</sub>/SiO<sub>2</sub> stacked dielectric are explored in this letter. The crystalline TiO<sub>2</sub> possesses a high permittivity while the SiO<sub>2</sub> provides a negative quadratic voltage coefficient of capacitance (<i>VCC</i>-α) to cancel out the positive <i>VCC</i>-α from the crystalline TiO<sub>2</sub>. These desirable properties render MIM capacitors with high performance in terms of a capacitance density of 11.9 fF/μm<sup>2</sup> with a <i>VCC</i>-α of 90 ppm/V<sup>2</sup>. With additional N<sub>2</sub> plasma treatment on the crystalline TiO<sub>2</sub>, because of the effective passivation of grain-boundary-related defects and, consequently, a lower leakage current by a factor of 50, the <i>VCC</i>-α can be further lowered to 30 ppm/V<sup>2</sup> with slight degradation in capacitance density to 11.2 fF/μm<sup>2</sup>, which well meets the requirement in 2018 set by ITRS.


IEEE Electron Device Letters | 2011

as Charge-Trapping Layer

Yung-Hsien Wu; Chia-Chun Lin; Yao-Chung Hu; Min-Lin Wu; Jia-Rong Wu; Lun-Lun Chen

Metal-insulator-metal (MIM) capacitors with single TiO<sub>2</sub> and a TiO<sub>2</sub>/Y<sub>2</sub>O<sub>3</sub> stack as an insulator are explored in this letter. It is found that, at the process temperature higher than 400°C, TiO<sub>2</sub> MIM capacitors demonstrate a high capacitance density at the price of an unacceptably high leakage current and voltage coefficient of capacitance (VCC). On the other hand, with the process temperature of 500°C, TiO<sub>2</sub>/Y<sub>2</sub>O<sub>3</sub> MIM capacitors display desirable characteristics in terms of a large capacitance density of 32.2 fF/μm<sup>2</sup>, a low VCC of 3490 ppm/ V<sup>2</sup>, small frequency dispersion, and a low leakage current of 4.5 × 10<sup>-9</sup> A/cm<sup>2</sup> at -1 V. The Y<sub>2</sub>O<sub>3</sub> film not only provides a high dielectric-electrode band offset but also possesses high thermal stability against crystallization; both are important to suppress leakage current. In addition, the Y<sub>2</sub>O<sub>3</sub> film prevents a TiO<sub>2</sub> film from crystallization at 500°C due to the increased entropy caused by incorporated Y atoms, and the amorphous TiO<sub>2</sub> film offers a high κ value to achieve a large capacitance density without sacrificing leakage current and VCC.


IEEE Electron Device Letters | 2012

Tetragonal

Yung-Hsien Wu; Jia-Rong Wu; Chin-Yao Hou; Chia-Chun Lin; Min-Lin Wu; Lun-Lun Chen

Resistive random access memory (RRAM) cells with a thin oxygen-deficient ZrTiOx, film topped by a Ti oxygen- gettering layer and a Pt electrode were fabricated on n-Ge layer, and the switching mechanism, as well as electrical characteristics, was explored. The RRAM cells demonstrate a stable bipolar switching behavior without the requirement of a forming process. Because of the existence of a larger amount of interface traps which would trap carriers and help build a favorable electric field for the drift of oxygen vacancies, the RRAM cells possess lower SET and RESET voltages compared to those fabricated on n-Si layer. With many promising properties such as a large sensing margin of 300 times, a high operation speed of 250 ns, a robust endurance of 105 cycles, and a long data retention time of up to 10 years, the ZrTiOx-based RRAM cells exhibit a promising perspective as nonvolatile memory devices for Ge-based technology.

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Yung-Hsien Wu

National Tsing Hua University

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Min-Lin Wu

National Tsing Hua University

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Jia-Rong Wu

National Tsing Hua University

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Chia-Chun Lin

National Tsing Hua University

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Rong-Jhe Lyu

National Tsing Hua University

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Yao-Chung Hu

National Tsing Hua University

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Yuan-Sheng Lin

National Tsing Hua University

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Chia-Hsuan Chang

National Tsing Hua University

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Chin-Yao Hou

National Tsing Hua University

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Bo-Yu Chen

National Tsing Hua University

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