Jia-Rong Wu

High-performance metal-insulator-metal capacitor with Ge-stabilized tetragonal ZrO2/amorphous La-doped ZrO2 dielectric

A Ge-stabilized tetragonal ZrO2 dielectric with a permittivity (κ) value of 36.5 has been obtained by annealing a ZrO2/Ge/ZrO2 laminate at 500 °C and it is a more reliable approach toward stabilizing a tetragonal ZrO2 film. However, metal-insulator-metal (MIM) capacitors with the sole tetragonal ZrO2 film as an insulator achieve a high capacitance density of 27.8 fF/μm2 at the price of a degraded quadratic voltage coefficient of capacitance (VCC) of 81 129 ppm/V2 and unacceptably high leakage current. By capping an amorphous La-doped ZrO2 layer with a κ value of 26.3 to block grain boundaries-induced leakage paths of the crystalline ZrO2 dielectric, high-performance MIM capacitors in terms of a capacitance density of 19.8 fF/μm2, a VCC of 3135 ppm/V2, leakage current of 6.5×10−8 A/cm2 at −1 V, as well as a satisfactory capacitance change of 1.21% after ten-year operation can be realized.

Impact of fluorine treatment on Fermi level depinning for metal/germanium Schottky junctions

CF4 plasma treatment on germanium (Ge) surface is proposed in this work to alleviate the strong Fermi level pinning between metal/Ge, and its effectiveness is also explored for n- and p-type Ge wafers. It is found that samples with CF4 plasma treatment reveal conduction behavior transition between Schottky and ohmic characteristics, a metal-work-function-dependent Schottky barrier height as well as modulated contact resistance, and these results confirm the depinning of Fermi level. This depinning can be explained by the effective capability in passivating dangling bonds at Ge surface through fluorine atoms and the formation of Ge-F binding with partial ionic property, both of which are helpful in decreasing the number of surface states and consequently release the pinning effect.

Ge-stabilized tetragonal ZrO2 as gate dielectric for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate

A Ge-stabilized tetragonal ZrO2 (t-ZrO2) film formed by incorporating Ge atoms thermally driven from an underlying Ge layer into a ZrO2 film was investigated as the gate dielectric for Ge metal-oxide-semiconductor (MOS) capacitors fabricated on a Si substrate. A sole t-ZrO2 film on Ge is not eligible for the gate dielectric because of the poor interface quality. By using a thermally-grown ultrathin GeO2 film as an interfacial layer, the t-ZrO2/GeO2/Ge stack shows improved interface characteristics and a permittivity (κ) value of 36.6 for the t-ZrO2. In addition, the stack also demonstrates good leakage current since the amorphous GeO2 layer terminates grain boundary channels in the crystalline ZrO2. Further leakage current suppression can be achieved by a H2 annealing of the t-ZrO2/GeO2/Ge stack since the defects at grain boundaries can be effectively passivated, which makes a leakage current of 1.08×10−6 A/cm2 at VFB−1 V for effective oxide thickness of 1.66 nm and paves an alternative avenue to develop ...

Nonvolatile Memory With Nitrogen-Stabilized Cubic-Phase

A cubic ZrO2 film formed by annealing of amorphous ZrON has been investigated as the charge-trapping layer for nonvolatile memory. The memory with a nitrogen-stabilized cubic ZrO2 film shows promising performance in terms of 3.81-V hysteresis memory window by ± 7-V program/erase voltage and 1.98-V flatband-voltage shift by programming at +7 V for 10 ms. As compared to that with an amorphous ZrON film, the improved performance is due to the greatly enhanced κ-value of 32.8 and the increased trapping sites provided by grain boundaries. Additionally, it shows 28.6% charge loss after ten-year operation at 85°C. Although it is worse than that with an amorphous ZrON film, it is advantageous over an atomic-layer-depositiongrown tetragonal ZrO2 film in terms of reduced leakage current. Improved retention can be accomplished by passivation of grain boundaries and/or high- κ double quantum barrier as the tunnel and blocking dielectric.

\hbox{ZrO}_{2}

By adopting an amorphous Y2O3 passivation layer, which provides a wide band gap and well passivates Ge surface without the presence of GeOx, a high-permittivity (κ) crystalline ZrO2/Y2O3 stack was explored as the gate dielectric for Ge metal-oxide-semiconductor (MOS) devices on Si substrate. The crystalline ZrO2 is a Ge stabilized tetragonal/cubic dielectric with the κ value of 36.1 and was formed by depositing a ZrO2/Ge/ZrO2 laminate and a subsequent 500 °C annealing. The high-κ crystalline ZrO2/Y2O3 gate stack shows promising electrical characteristics in terms of low interface trap density of 5.8×1011 cm−2 eV−1, negligible hysteresis, and leakage current of 5.6×10−4 A/cm2 at gate bias of flatband voltage (VFB) 1 V for equivalent oxide thickness of 1.13 nm. This gate stack not only demonstrates the eligibility for advanced Ge MOS devices but introduces a more reliable process to form a high-κ crystalline gate dielectric.

as Charge-Trapping Layer

Metal-insulator-metal (MIM) capacitors with crystalline-TiO₂/SiO₂ stacked dielectric are explored in this letter. The crystalline TiO₂ possesses a high permittivity while the SiO₂ provides a negative quadratic voltage coefficient of capacitance (<i>VCC</i>-α) to cancel out the positive <i>VCC</i>-α from the crystalline TiO₂. These desirable properties render MIM capacitors with high performance in terms of a capacitance density of 11.9 fF/μm² with a <i>VCC</i>-α of 90 ppm/V². With additional N₂ plasma treatment on the crystalline TiO₂, because of the effective passivation of grain-boundary-related defects and, consequently, a lower leakage current by a factor of 50, the <i>VCC</i>-α can be further lowered to 30 ppm/V² with slight degradation in capacitance density to 11.2 fF/μm², which well meets the requirement in 2018 set by ITRS.

Crystalline ZrO2-gated Ge metal-oxide-semiconductor capacitors fabricated on Si substrate with Y2O3 as passivation layer

Metal-insulator-metal (MIM) capacitors with single TiO₂ and a TiO₂/Y₂O₃ stack as an insulator are explored in this letter. It is found that, at the process temperature higher than 400°C, TiO₂ MIM capacitors demonstrate a high capacitance density at the price of an unacceptably high leakage current and voltage coefficient of capacitance (VCC). On the other hand, with the process temperature of 500°C, TiO₂/Y₂O₃ MIM capacitors display desirable characteristics in terms of a large capacitance density of 32.2 fF/μm², a low VCC of 3490 ppm/ V², small frequency dispersion, and a low leakage current of 4.5 × 10^-9 A/cm² at -1 V. The Y₂O₃ film not only provides a high dielectric-electrode band offset but also possesses high thermal stability against crystallization; both are important to suppress leakage current. In addition, the Y₂O₃ film prevents a TiO₂ film from crystallization at 500°C due to the increased entropy caused by incorporated Y atoms, and the amorphous TiO₂ film offers a high κ value to achieve a large capacitance density without sacrificing leakage current and VCC.

MIM Capacitors With Crystalline-

Resistive random access memory (RRAM) cells with a thin oxygen-deficient ZrTiOx, film topped by a Ti oxygen- gettering layer and a Pt electrode were fabricated on n-Ge layer, and the switching mechanism, as well as electrical characteristics, was explored. The RRAM cells demonstrate a stable bipolar switching behavior without the requirement of a forming process. Because of the existence of a larger amount of interface traps which would trap carriers and help build a favorable electric field for the drift of oxygen vacancies, the RRAM cells possess lower SET and RESET voltages compared to those fabricated on n-Si layer. With many promising properties such as a large sensing margin of 300 times, a high operation speed of 250 ns, a robust endurance of 105 cycles, and a long data retention time of up to 10 years, the ZrTiOx-based RRAM cells exhibit a promising perspective as nonvolatile memory devices for Ge-based technology.

\hbox{TiO}_{2}/ \hbox{SiO}_{2}

With the Si substrate, a process to fabricate Ge metal-oxide-semiconductor (MOS) capacitors with thermally grown SiO2 as the gate dielectric has been presented. The good crystallinity of the epitaxial Ge, the thermal oxide with tiny Ge content, and the smooth interface between oxide and Ge layer demonstrate the eligibility for device operation. From the electrical characterization of the MOS capacitors, enhanced dielectric constant of the gate oxide without deteriorating the leakage current and hysteresis can be achieved by proper NH3 nitridation and subsequent N2O treatment which shows the high potential to be employed in the fabrication of high performance Ge metal-oxide-semiconductor field-effect transist.

Stack Featuring High Capacitance Density and Low Voltage Coefficient

With a Si substrate, the p-MOSFET formed on a thin Ge layer with the thermal SiON as the gate dielectric was electrically characterized in this letter. The desirable passivation of the Ge channel is evidenced by the interface trap density lower than 3.46 times1011 cm-2middoteV-1. A 1.74 times higher peak hole mobility than that of the Si universal one is obtained by the Ge MOSFET due to the low interface trap density and the good Ge crystallinity. With the source/drain region mainly formed on the Si substrate, the Ge MOSFET also demonstrates the excellent junction leakage. Combining these promising electrical characteristics, the thermal SiON with the device structure holds the potential to be applied to high-performance Ge MOSFETs.