Yuanyuan V. Li

Low-Voltage Double-Gate ZnO Thin-Film Transistor Circuits

In this letter, we report double-gate ZnO thin-film transistor (TFT) circuits deposited by plasma-enhanced atomic layer deposition that are suitable for low-voltage operation. Compared to bottom-gate-only ZnO TFTs, double-gate ZnO TFTs have improved mobility, subthreshold slope, and bias stability. In this letter, the TFT top gate is used to adjust the bottom-gate turn-on and threshold voltage. This allows the logic transition point for circuits to be adjusted for operation at a low voltage. Using this approach, high-gain inverters (gain >100) and low-voltage ring oscillators using double-gate TFTs have been demonstrated. Double-gate inverters with a beta ratio of 5 have a gain larger than 100. Fifteen-stage double-gate ZnO TFT ring oscillators operate with VDD = 1.5 V, ID = 28 μA, and propagation delay of 2 μs per stage.

Passivation of ZnO TFTs

— The impact of passivation processes on ZnO thin-film transistors is reported. In general, passivation processes result in back-channel doping, which corresponds to shifts in threshold voltage and changes in subthreshold slope. It was determined that ALD-based passivation results in considerably smaller undesirable shifts than those observed with plasma-based processes. Two approaches, one a bulk doping with ammonia and the other a surface treatment with hydrogen peroxide, to further mitigate the detrimental effects of the passivation process are described. After proper passivation, ZnO devices show negligible hysteresis, have excellent stability to bias stress, and maintain or improve the good transport properties of as-deposited devices. Although the existence of grain boundaries has been assumed to be a point of concern for device stability in polycrystalline metal oxides, no evidence was found to suggest that the grain boundaries present in these ZnO thin-film transistors have affected the device stability.

pH-Controlled Selective Etching of Al2O3 over ZnO

We describe pH-controlled selective etching of atomic layer deposition (ALD) Al2O3 over ZnO. Film thickness as a function of etch exposure was measured by spectroscopic ellipsometry. We find that alkaline aqueous solutions with pH between about 9 and 12 will etch Al2O3 at useful rate with minimal attack of ZnO. Highly selective etching of Al2O3 over ZnO (selectivity >400:1) and an Al2O3 etch rate of ∼50 nm/min can be obtained using a pH 12 etch solution at 60 °C.

Trilayer ZnO Thin-Film Transistors With In Situ

In this letter, we report trilayer ZnO thin-film transistors (TFTs) with in situ Al₂O₃ passivation fabricated using plasma-enhanced atomic layer deposition. The bottom-gate, top-contact TFTs use an Al₂O₃-ZnO-Al₂O₃ trilayer deposited in one deposition run at 200°C that provides protection for the active layer back surface with no extra passivation step. Compared with Al₂O₃ passivated, nontrilayer ZnO TFTs, these trilayer devices have similar field effect mobility, but more positive turn-on voltage and improved bias stability. Seven-stage trilayer ZnO TFT ring oscillators operated at 3.5 MHz at a supply voltage of 17 V, corresponding to a propagation delay of ~ 27 ns/stage.

{\rm Al}_{2}{\rm O}_{3}

We report effects for up to 100 Mrad (SiO2) gamma-ray exposure on polycrystalline ZnO thin film transistors (TFTs) deposited by two different techniques. The radiation related TFT changes, either with or without electrical bias during irradiation, are primarily a negative VON shift and a smaller VT shift (ΔVON ~ - 2.5 V and ΔVT ~ - 1.5 V for 100 Mrad (SiO2) exposure). Field-effect mobility remains nearly unchanged. Both, VON and VT shifts are nearly completely removed by annealing at 200°C for 1 minute and some recovery is seen even at room temperature. We find that our ZnO TFTs are insensitive to electrical bias during irradiation; that is, unbiased measurements are useful worst case test results. To the best of our knowledge, these are the most radiation-hard thin film transistors reported to date.

Passivation

Radiation tolerance is of interest in electronic applications such as radiation sensors, nuclear reactors, x-ray imagers, and high-energy particle accelerators. While properly designed Si MOSFETS are usefully radiation resistant, most thin-film transistors (TFTs), including polysilicon and a-Si:H, are severely degraded by relatively low irradiation dose (typically <;1 Mrad) [1, 2]. We previously reported gamma ray radiation exposure results for unbiased ZnO TFTs and circuits and found only small electrical changes for doses up to 100 Mrad [3]. For applications with TFTs operating in harsh radiation environments, the effects of simultaneous electrical stress and radiation exposure are important. We report here the effects of 60Co gamma irradiation and electrical stress on the characteristics of ZnO TFTs with active and dielectric layers deposited by weak-oxidant plasma enhanced atomic layer deposition (PEALD).

Radiation-Hard ZnO Thin Film Transistors

Radial junction Si pillar array solar cells based on the heterojunction with intrinsic thin layer (HIT) structure were fabricated from p-type crystal Si (c-Si) wafers of different doping densities. The HIT structure consisting of intrinsic/n-type hydrogenated amorphous Si (a-Si:H) deposited by plasma-enhanced chemical vapor deposition (PECVD) at low temperature (200°C) was found to effectively passivate the high surface area of the p-type Si pillar arrays resulting in open circuit voltages (Voc>0.5) comparable to that obtained on planar devices. At high c-Si doping densities (>1018 cm-3), the short-circuit current density (Jsc) and energy conversion efficiency of the radial junction devices were higher than those of the planar devices demonstrating improved carrier collection in the radial junction structure.

Effects of gamma-ray irradiation and electrical stress on ZnO thin film transistors

We report here double-gate ZnO thin film transistor (TFT) circuits with operation at low voltage. TFTs with low voltage operation have been reported previously, but often use very thin (few nm thick) gate dielectric which may limit manufacturability. Oxide semiconductor-based TFTs have been extensively studied as competitive candidates for next-generation display technology and other large-area electronics. For many applications, operation at voltages compatible with low-voltage CMOS is important. Doublegate TFTs are of interest because they allow threshold voltage tuning, improved device performance, and circuit applications like mixers. We have previously reported bottom-gate ZnO TFTs and circuits fabricated on glass and flexible polymeric substrates using plasma enhanced atomic layer deposition (PEALD). Here we report double-gate ZnO TFTs and circuits fabricated on glass substrates using PEALD with a maximum process temperature of 200 °C. Compared to bottom-gate ZnO TFTs, doublegate ZnO TFTs have higher mobility, and reduced substhreshold slope. In these devices, the top gate can be used to vary the bottom-gate threshold voltage by more than 4 V. This allows the logic transition point for circuits to be adjusted as desired and allows logic operation at low voltage. 15 stage double-gate ZnO TFT ring oscillators operate well with VDD = 1.2 V, ID = 32 μA, and propagation delay of 2.1 μs/stage.

Effect of c-Si doping density on heterojunction with intrinsic thin layer (HIT) radial junction solar cells

Oxide semiconductor electronics may enable new applications including large-area, flexible, integrated systems. ZnO thin film transistors have been reported with field-effect mobility > 100 cm²/V·s, on-current density > 700 mA/mm, and microwave operation (f<inf>T</inf> > 2 GHz, f<inf>max</inf> > 7 GHz) for ZnO deposited by pulsed laser deposition at 400°C.[1] Other oxide semiconductors, including amorphous and crystalline mixtures of I<inf>2</inf>O<inf>3</inf>, Ga<inf>2</inf>O<inf>3</inf>, ZnO, have also been widely studied, and high mobility (> 30 cm²/V·s) thin film transistors and circuits with propagation delays < 1 ns/stage have been reported.[2,3] However, most of these high performance demonstrations were done on single crystal semiconductor substrates with high thermal conductivity. Here we find that self-heating and not drain-induced barrier lowering as previously reported [1] is the physical mechanism responsible for the output conductance (g<inf>d</inf> = dI<inf>DS</inf>/dV<inf>DS</inf>) observed in a range of oxide thin film transistors. In particular we find that self-heating is a significant limiting factor for the performance of oxide devices and circuits on low-cost, low-thermal conductivity substrates such as glass and plastic.

Low-voltage ZnO double-gate thin film transistor circuits

We have fabricated ZnO thin film transistors (TFTs) on rigid and flexible substrates with characteristics well suited for displays and more general microelectronic applications. Using weak-reactant plasma enhanced atomic layer deposition (PEALD) we have fabricated single-gate, double-gate, and trilayer ZnO TFTs with good performance and stability. We have also fabricated TFTs and circuits on thin (few μm thick) solution-cast polymeric substrates that can be flexed to small radius for thousands of cycles.