Yuichiro Nanen

Effects of Nitridation on 4H-SiC MOSFETs Fabricated on Various Crystal Faces

Effects of nitric oxide (NO) and nitrous oxide (N₂O) annealing on 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on the (0001), (0001̅), and (112̅0) faces are investigated. MOSFETs on (112̅0) exhibited high channel mobility (108 cm²/V·s) compared to those on (0001) (29-37 cm²/V·s) and (0001̅) (39-46 cm²/V·s). The MOSFET characteristics are discussed in terms of oxidation taking place during the nitridation annealing and crystal faces.

Enhancement of Carrier Lifetimes in n-Type 4H-SiC Epitaxial Layers by Improved Surface Passivation

Carrier lifetimes in n-type 4H-SiC epitaxial layers are limited by several factors such as deep levels, surface recombination, and recombination in the substrate. In this study, the carrier lifetime is significantly improved from 0.68 to 13.1 µs by eliminating deep levels and by improving surface passivation. Deep levels can be almost eliminated by two-step annealing as reported before, and the surface recombination can be reduced by passivating the surface with a deposited oxide annealed in nitric oxide at 1300 °C. Major recombination paths are discussed based on numerical simulation.

Detection and Electrical Characterization of Defects at the SiO2/4H-SiC Interface

Two electrical measurement techniques are frequently employed for the characteri- zation of traps at the SiO2/SiC interface: the thermal dielectric relaxation current (TDRC) and the conductance method (CM). When plotting Dit as a function of the energy position Eit in the bandgap both techniques reveal comparable results for deep interface traps (ECEit > 0:3 eV). For shallower traps, CM always shows a strong increase of Dit which originates from near interface traps (NIT). TDRC provides a contradictory result, namely a slight decrease of Dit. In this paper, we show that the position of NITs in the oxide close to the interface is responsible for the invisibility of these traps in TDRC spectra. We further show that NITs become detectable by the TDRC method by using a discharging voltage Vdis close to the accumulation regime. However, due to the Shockley-Ramo-Theorem the contribution of NITs to the Dit in TDRC spectra is strongly suppressed and can be increased by using thin oxides.

Abnormal behavior of longitudinal optical phonon in silicon dioxide films on 4H-SiC bulk epitaxial substrate using Fourier transform infrared (FT-IR) spectroscopy.

We report the abnormal behavior of longitudinal optical (LO) phonon in a silicon dioxide (SiO2) film on a 4H-SiC bulk epitaxial substrate using an attenuated total reflection (ATR) technique. The peak frequency of the LO phonon in the ATR spectrum was observed at around 1165 cm−1 and red-shifted by approximately 92 cm−1 relative to that at the grazing incidence (40°), whereas the peak frequency of the transverse optical (TO) phonon in the ATR spectrum agreed well with that at the grazing incidence. Furthermore, the peak frequency of the TO phonon hardly depends on change in the incident angle and thickness, suggesting that the microstructure of the sample is homogeneous within a thickness of 100 nm. On the other hand, we found that the microstructure of the sample was inhomogeneous within a thickness less than 5 nm. Fourier transform infrared (FT-IR) spectroscopy provides us with a large amount of data on microstructures in the SiO2 films on a 4H-SiC substrate.

Improved Characteristics of SiC MOSFETs by Post-Oxidation Annealing in Ar at High Temperature

Post-oxidation annealing (POA) in Ar at high temperature has been performed during fabrication of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxides were formed by thermal oxidation followed by N2O annealing, then annealed in Ar for 30 min or 5 h at 1300 °C. The results of Secondary Ion Mass Spectrometry (SIMS) measurements indicated that the C atoms accumulated at the SiO2/SiC interface by thermal oxidation diffused during the 5h-Ar annealing. The characteristics of n-channel MOSFETs were improved and the peak value of field effect mobility was increased to 33 cm2/Vs from 19 cm2/Vs by extending the Ar annealing time.

Enhanced Drain Current of 4 H-SiC MOSFETs by Adopting a Three-Dimensional Gate Structure

4H-SiC (0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) with a 3-D gate structure, which has a top channel on the (0001) face and side-wall channels on the {112macr0} face, have been fabricated. The 3-D gate structures with a 1-5-mum width and a 0.8- mum height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300degC. The fabricated MOSFETs have exhibited good characteristics: The I ON/I OFF ratio, the subthreshold swing, and V TH are 109, 210 mV/decade, and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1-mum-wide MOSFET is 16 times higher than that of a conventional planar MOSFET.

Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices

We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (VFB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the VFB shift due to hole trapping was found to be suppressed by NO annealing. However, the VFB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.

Preannealing Effect on Mobility of N-/Al-Coimplanted and Over-Oxidized 4H-SiC MOSFETs

The authors investigated the effect of preannealing on N-/Al-coimplanted and over-oxidized Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). The preannealing process causes a decrease of the Hall mobility and the effective mobility, and an increase of the interface state density. Secondary ion mass spectroscopy (SIMS) measurements revealed that the N concentration at the SiO2/SiC interface in preannealed samples is lower than in not-preannealed samples, which might be the reason for in the increase of the interface state density. In MOSFETs without preannealing, more N atoms are piled up at the SiO2/SiC interface, leading to the lower interface state density and higher mobility.

Characterization of Inhomogeneity in Silicon Dioxide Films on 4H-Silicon Carbide Epitaxial Substrate Using a Combination of Fourier Transform Infrared and Cathodoluminescence Spectroscopy

We measured the Fourier transform infrared (FT-IR) and cathodoluminescence (CL) spectra of silicon dioxide (SiO2) films grown on 4H-silicon carbide (4H-SiC) substrates and confirmed that the phonon observed at around 1150-1250 cm−1 originates from the upper branch of the surface phonon polaritons (SPPs) in the SiO2 films and that its frequency is sensitive to the oxide thickness. The relative intensity of the upper branch of SPPs normalized by that of the transverse optical phonon (TO) tended to increase with decreasing channel mobility (CM). A comparison of the FT-IR and CL measurements shows that the relative intensity is correlated with an inhomogeneity in the SiO2–SiC interface and the CM of SiC devices. A combination of FT-IR spectroscopy and CL spectroscopy provides us with a large amount of data on the inhomogeneity, defect, and oxide thickness of SiO2 films on 4H-SiC substrates.

High-Temperature Characteristics of 3-kV 4H-SiC Reverse Blocking MOSFET for High-Performance Bidirectional Switch

Novel 3-kV 4H-SiC reverse blocking (RB) metal–oxide–semiconductor field-effect transistors (MOSFETs) have been demonstrated for high-voltage bidirectional switching applications. To achieve RB capability, a series Schottky barrier diode structure was introduced onto the backside of the 4H-SiC MOSFET. The developed SiC RB MOSFET exhibits bidirectional blocking voltage over 3 kV and a differential specific on-resistance of 20