Yuji Kihara

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

Voltage and technology scaling and increasing random variation in MOSFET characteristics reduce the operational margin of SRAM functionality, and several design techniques have been suggested to improve margins [1–3]. However, it is still difficult to achieve low-voltage operation (less than 1V) by design alone for devices such as sensor network applications using solar batteries. Design solutions combined with device techniques are required for robust SRAM operation and at the same time maintain low standby leakage.

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Showing that the worst minimum operating voltage (Vmin) of an 8T dual-port (DP) SRAM is determined by the write/read-disturbing condition with a finite clock skew, we propose a circuit technique to detect the worst Vmin in asynchronous clock operation. This circuitry allows us to screen the worst bit in an array that is conventionally obtained by a costly and time-consuming test procedure. For instance, we can at least realize 400x speed-up for the test time compared to the conventional method. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed experimentally that the worst Vmin can be successfully reproduced within 6% discrepancy by our proposed circuit.

A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues

We propose a circuit technique for an 8T dual-port (DP) SRAM in order to screen degraded minimum operating voltage (V min ) due to the write/read disturb issue. This circuitry allows us to generate the write/read disturb condition without relying on the conventional costly asynchronous operation. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed assured screening of failures in the write/read disturb operations.

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs

We discuss dynamic stability for single-port SRAM that manifests itself in the difference between minimum operating voltage (Vmin) for longer and shorter word-line (WL) pulse width (Twl). The most probable failure points (MPFPs) that determine Vmin for various Twl are investigated. Regarding dual-port SRAM, we identify the MPFP for the worst Vmin degraded by WL pulse skew between ports in asynchronous operation. The validity of our simulation results are verified through comparison with measured data for SRAM modules in 28 nm generation.

A 16M SRAM with improved characteristics using DRAM technology

A 16Mbit low power SRAM with 0.98mum2 cells using 0.15mum DRAM and TFT technology has been developed. A new type memory cell technology achieves enough low power, low cost and high soft error immunity without large investment. By these improved characteristics some customers at industrial machines and handy devices decided to use this new type of SRAM by compatibility with SRAM

A 100MHz dual port (DP) MRAM with swing-less bit-line sensing (SLBS) operation for high-end microcomputer systems

In this paper, we propose two kinds of implementations of the dual port MRAM, one of which is for the read/write concurrent operation while another is for the additional simultaneous read operation. Compared with dual port SRAM, the dual port MRAM accompanied with smaller memory cell size will make high performance systems realized in the mobile/robotics field. A swing-less bit-line sensing (SLBS) technique and the static bitline level in the read mode, help to realize the high performance under the condition of Vcc=1.0 V and the operation frequency of 100 MHz