Yukinobu Murao

A Room Temperature Chemical Vapor Deposition SiOF Film Formation Technology for the Interlayer in Submicron Multilevel Interconnections

A new interlayer dielectric film formation technology for multilevel interconnection by catalytic chemical vapor deposition has been developed. This technique utilizes fluorotriethoxysilane and water vapor as gas source. The films deposited at 25°C have remarkably good properties, such as tightly bonded Si‐O networks with no OH radicals, large density value (2.20 g/cm3), small residual stress (50 MPa), low leakage current, and small dielectric constant (3.7), although the film contains residual fluorine and carbon atoms with , respectively. Based on the film characterization results, we speculate that the reaction sequence for the film deposition is: hydrolysis of fluorotriethoxysilane monomers, formation of siloxane oligomers with reaction by‐product (alcohol), adsorption of the oligomers to the wafer surface, and then polymerization. The electrical conduction mechanism study revealed that the Schottky emission was dominant for the electric conduction through the film. It also has clarified that the deposition film thickness has no dependence on Al wiring widths, and is completely isotropic with no crack or keyhole in the film.

A Selective SiO2 Film‐Formation Technology Using Liquid‐Phase Deposition for Fully Planarized Multilevel Interconnections

A selective SiO 2 film-formation technology using liquid-phase deposition (LPD) around room temperature for fully planarized multilevel interconnections is developed. The LPD technique utilizes supersaturated hydrofluosilicic acid (H 2 SiF 6 ) aqueous solution as a source liquid. The LPD-SiO 2 films can be selectively formed on chemical vapor deposition (CVD) SiO 2 underlayers in the trenches between photoresist patterns or tungsten wiring with photoresist as mask. For polysilicon patterns with photoresist masks, the LPD-SiO 2 films creep along the polysilicon and photoresist sidewalls

An asymmetric sidewall process for high performance LDD MOSFET's

An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined. >

Stability of a new polyimide siloxane film as interlayer dielectrics of ULSI multilevel interconnections

Abstract Stability of a new polyimide siloxane (PSI) film as interlayer dielectrics of ULSI multilevel interconnections is studied. The PSI films, involving Si-phenyl bonds, are designed to have a three-dimensional polymer structure by crosslinking through Si-O bonds. It has been revealed that the PSI films are more stable than conventional polyimide films in terms of thermal and electrical properties at high temperatures. The PSI films decomposition temperature is as high as 500°C. The coefficient of thermal expansion is 4 × 10−5 K−1 in the temperatures of 25–450°C. The abrupt thermal expansion that usually occurs at around 270°C for conventional polyimide films is eliminated. The residual stress for the PSI films is less than 20 MPa, and is lower than for conventional polyimide films. Leakage currents through the PSI films at temperatures above 100°C are over one order of magnitude lower than those through conventional polyimide films. Good surface planarization characteristics are obtained for the PSI films by decreasing the molecular weight and viscosity of the polyamic acid solutions. No void is observed acid the films formed on 2.4 μm thick silicon dioxide lines with 1.1 μm width and 1.5 μm spacing, using polyamic acid solutions with precursor molecular weights ranging from 2900 to 9600.

A new interlayer formation technology for completely planarized multilevel interconnection by using LPD

A description is given of a newly developed selective interlayer dielectrics formation technology to realize completely planarized multilevel interconnections. The technology uses liquid phase deposition (LPD) at extremely low temperature (~40°C). This technology has the capability to realize high density VLSIs such as logic devices beyond 100-kgate and memory devices beyond 16-Mb because of the low thermal stress and the excellent planarization characteristics. This technology eliminates key hole formation in spacings among wirings. Selective deposition is possible by LPD. Compared with conventional CVD films, the LPD-SiO2 film has excellent properties for interlayer dielectrics. A completely planarized two-level interconnection using the LPD technology is discussed

A Spin‐on‐Glass Film Treatment Technology Using a Fluoroalkoxysilane Vapor at Room Temperature

A spin‐on‐glass (SOG) film modification technology, using a fluoroalkoxysilane vapor treatment (FAST) at room temperature, is developed. The silanol‐based SOG films with the thickness of about 0.25 μm can be modified by the fluorotriethoxysilane (FTES) monomers, and their properties are improved with increasing the FAST time. It has been revealed that the fluorine atoms are deeply and uniformly distributed across the modified SOG films. It has also been clarified that the modified SOG films have tightly bonded Si‐O networks with less residual OH radical than those without the FAST process. At the FAST time of 120 min, the modified SOG films refractive index is 1.398, density is 2.20 g/cm3,, and shrinkage is −5% (increase). The hypothetical mechanism of the FAST is: fluoroalkoxysilane monomers are diffused into the SOG films, adsorbed to the Si‐OH bonds existing in the SOG precursors, then the precursors are cross‐linked with assistance of FTES monomers by a catalytic dehydration reaction at room temperature. Warpage variations for a 500 μm thick, 4 in. Si wafer with a 0.25 μm thick modified SOG film in a heating cycle with the temperatures ranging from 25 to 430°C are less than 2.1 μm which is three times smaller than those without the FAST process (6.3 μm). The moisture absorbed in the modified SOG films is about 2 weight percent (w/o) which is eight times smaller than that without the FAST process (16 w/o). The leakage current through the films, measured using an Al/SOG film/p‐Si structure (−5 V to Al) decreases with increasing the FAST time. The leakage current at the FAST time of 120 min is about three orders of magnitude smaller than those without the FAST process. The FAST technique has been applied to interlayer dielectric film planarization of a double level Al interconnection without using any SOG etchback process, where pure Al is used as wiring materials. The surface planarization characteristics are better than those using the conventional SOG etchback process. Neither crack nor void is observed in the trenches between the Al wirings. For the double level Al interconnections formed on 4 in. Si wafers, via hole resistances and yields, which have been obtained from five wafers with 100 chips of 10,000 via chains on each wafer, are 0.11 to 0.13 Ω/unit and 98%, respectively. The via hole diameter in this experiment is 0.9 μm. The via hole resistance increase and open circuit, which are very common in the conventional SOG planarization process without using any SOG etchback, has not been observed for the double level Al interconnections, even without using any SOG etchback process.

Properties of liquid-phase-deposited SiO2 films for interlayer dielectrics in ultralarge-scale integrated circuit multilevel interconnections

Abstract Properties of a new fluorinated SiO2 film for interlayer dielectrics in multilevel interconnections of ultralarge-scale integrated circuits (ULSIs) are investigated. The fluorinated SiO2 films are formed at 35 °C by a liquid phase deposition (LPD) technique using a supersaturated hydrofluosilicic acid (H2SiF6) aqueous solution. The LPD SiO2 film surface profiles on polysilicon and aluminum wirings are flat enough, indicating that the LPD technique has good capability for the surface planarization of interlayer dielectric films. The compositions of as-deposited LPD SiO2 films and those annealed at 400 and 900 °C are SiO1.85F0.15, SiO1.85F0.15 and SiO1.90F0.10 respectively. The LPD SiO2 film deposition mechanism is explained as follows: (i) fluorosilanols [FnSi(OH)4−n] formation; (ii) fluorosilanol oligomer formation by a catalytic reaction in the solution; (iii) oligomer adsorption onto the substrate surface; (iv) oligomer polymerization by a catalytic reaction. The absorption peak position, full width at half-maximum (FWHM) and absorption coefficient for the Si-O bond in the Fourier transform infrared spectra for the as-deposited LPD SiO2 films are 9.17 micrometer, 0.83 micrometer and 1.19 × 106 m-1, respectively, indicating that the films are formed by tightly bonded Si-O networks. The as-deposited LPD SiO2 films have a refractive index of 1.433, a density of 2.19 × 103 kg m-3, an etching rate (measured using 1:30 buffered hydrofluoric acid (HF) solution) of 83 nm min-1, and a residual stress of 20 MPa (tensile). The film shrinkages after annealing at 400 and 900 °C are 0.8% and 2.0% respectively. Although these properties are changed by annealing at 400 and 900 °C, these values are still better than those of SiO2 films deposited by chemical vapor deposition (CVD) at 400 °C for use as interlayer dielectric films. The LPD SiO2 films have better electrical properties, such as lower leakage current, higher dielectric breakdown strength (> 6.3 × 108 V m-1) and lower dielectric constant (

A 7-mask CMOS process with selective oxide deposition

A seven mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist is described. The process modules for self-aligned well and one-mask LDD formation are developed. The features of the process are: (1) short TAT (7 masks to first metallization), (2) self-aligned twin retrograde wells with 40% reduction of the p/sup +/-n/sup +/ spacing compared to conventional wells, and (3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFETs giving a 10% larger on-current for p-channel MOSFETs compared to a conventional process. >

A 7 mask CMOS-technology utilizing liquid phase selective oxide deposition

The authors describe a fully symmetric 7 mask CMOS technology, utilizing a room-temperature liquid phase oxide deposition technique which has selectivity against photo resist. They have developed process modules for self-aligned well and one mask LDD (lightly doped drain) formation which achieve excellent device performance. The main features of this CMOS technology are (1) very short processing time: (7 masks to first metallization); (2) self-aligned twin retrograde wells with 40% reduction of p/sup +/-n/sup +/ spacing; and (3) optimal LDD design using different-width side-wall spacers for n- and p-channel MOSFETs with a 10% larger on current for p-channel MOSFETs.<<ETX>>

Adhesion layerless submicron Al damascene interconnections using novel Al-CVD

Adhesion layerless submicron damascene interconnection has been realized by using a combination of novel Al-CVD and CMP technique. A new nucleation method with tetrakis-dimethyl-amino titanium (TDMAT) gas pretreatment has enabled Al-CVD to fill Al in trenches without using a glue layer. As a result, this technology achieved Al damascene interconnections with low specific line resistance as low as 600 /spl Omega//cm with half micron line width and an aspect ratio of 3. This specific line resistance is one-third of that for conventional reactive ion etched Al line with an aspect ratio of 1.<<ETX>>