Koichiro Okumura

An asymmetric sidewall process for high performance LDD MOSFET's

An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined. >

Activation energy for the C49‐to‐C54 phase transition of polycrystalline TiSi2 films with arsenic impurities

The C49‐to‐C54 transition in TiSi2 was investigated using samples having submicron line width film, by an x‐ray diffraction technique. Arrhenius plots of the transition rate show that the C49‐to‐C54 transition of polycrystalline TiSi2 films with arsenic impurities have an activation energy barrier strongly dependent on the arsenic concentration. The energy increases as a function of arsenic impurity concentration, from 3.5 eV for TiSi2 formed on Si substrate ion implanted with the dose of 2×1015 cm−2, to 7.8 eV with the dose of 5×1015 cm−2. The annealing time dependence of the x‐ray intensity on (004) orientation indicates that TiSi2 formed on Si substrate with the arsenic dose of 2×1015 cm−2 shows a diffusion‐limited process and that with the dose of 5×1015 cm−2 shows an interface‐limited process. The arsenic precipitates act to pin the C49 phase in the C49‐to‐C54 transition.

A 7-mask CMOS process with selective oxide deposition

A seven mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist is described. The process modules for self-aligned well and one-mask LDD formation are developed. The features of the process are: (1) short TAT (7 masks to first metallization), (2) self-aligned twin retrograde wells with 40% reduction of the p/sup +/-n/sup +/ spacing compared to conventional wells, and (3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFETs giving a 10% larger on-current for p-channel MOSFETs compared to a conventional process. >

Front- and Back-Interface Trap Densities and Subthreshold Swings of Fully Depleted Mode Metal-Oxide-Semiconductor Transistors Fabricated on Separation-by-Implanted-Oxygen Substrates

By measuring the charge pumping current (ICP) and the subthreshold swing, we examined the front- and back-interface trap densities (Dfit and Dbit) of long channel N-type metal-oxide-semiconductor transistors fabricated on separation-by-implanted-oxygen (SIMOX) substrates, as a function of the total oxygen implantation dose. The front-channel subthreshold swing (Sf) measured in the coupled condition was larger than that calculated with Dfit and Dbit obtained from ICP. However, dose dependences of the Dfit and Dbit obtained from ICP were consistent with those of the front- and back-channel peak mobilities, while those obtained from the subthreshold swings were not. These seemingly contradictory results can be satisfactorily explained by the existence of lateral nonuniformities (LNU) in the front- and the back-channel local threshold voltages. We propose that the experimentally determined Sf can be used as an index of LNU in the SIMOX and other silicon-on-insulator substrates, just by comparing it with the theoretical value of Sf.

Comparison of fully depleted and partially depleted mode transistors for practical high-speed, low-power 0.35 /spl mu/m CMOS/SIMOX circuits

Although attractive features of fully depleted mode transistors have already been clarified, essential roles of the fully depleted mode itself in improved performance of digital circuits have not been shown clearly. In this study, we examined such parameters as the propagation delay time and power consumption of 0.35-/spl mu/m CMOS/SIMOX gates (inverter, 2-6NAND, 2-6NOR) composed of fully depleted (FD), near fully depleted (n-FD), or partially depleted (PD) mode transistors with no body-contacts, and discussed the essentially important factors for high performances of CMOS/SIMOX circuits.

TiN-capped TiSi2 formation in W/TiSi2 process for a quarter-micron complementary metal-oxide-semiconductor

Abstract We have investigated the diffusion of nitrogen and oxygen into TiSi 2 through a thermally formed TiN capped layer. We have observed that nitrogen diffuses through the TiN capped layer into the TiSi 2 layer at temperatures above 200 °C, but oxygen diffuses into TiSi 2 through the TiN capped layer at temperatures above 400 °C. Both oxygen and nitrogen in the TiSi 2 film increase the C49-to-C54 phase transition temperature, and also degrade the morphology of selectively deposited tungsten films.

A 7 mask CMOS-technology utilizing liquid phase selective oxide deposition

The authors describe a fully symmetric 7 mask CMOS technology, utilizing a room-temperature liquid phase oxide deposition technique which has selectivity against photo resist. They have developed process modules for self-aligned well and one mask LDD (lightly doped drain) formation which achieve excellent device performance. The main features of this CMOS technology are (1) very short processing time: (7 masks to first metallization); (2) self-aligned twin retrograde wells with 40% reduction of p/sup +/-n/sup +/ spacing; and (3) optimal LDD design using different-width side-wall spacers for n- and p-channel MOSFETs with a 10% larger on current for p-channel MOSFETs.<<ETX>>

A new titanium salicide process (DIET) for sub-quarter micron CMOS

This paper describes a new one-step annealing TiSi/sub 2/ process which achieves a 0.2 /spl mu/m line silicidation without causing the agglomeration and uncompleted phase transition failure. The process consists of i) one-step silicidation at over 800/spl deg/C which reduces C49-to-C54 phase transition temperature and ii) TiSi/sub 2/ over-growth control by a thin Ti and pre-amorphized Si reaction.<<ETX>>

Plasma-induced gate oxide degradation and its impact on oxide reliability for CMOS FETs

Plasma-induced gate oxide degradation has been investigated using CMOS device structures, as well as single-channel MOSFETs. The plasma process induces both interface states and oxide charges in n-ch and p-ch MOSFETs. Although forming gas anneal recovers or masks most of the damage, the damage reappears in the form of reduced hot carrier reliability. The study of dual-gate MOSFETs, in which an antenna aluminum-pad is shared by n-ch and p-ch MOSFETs, shows that the plasma charges collected by the antenna are equally divided between n-ch and p-ch MOSFETs. This indicates that the nature of the plasma stress acting on MOS devices is more like a current source. It was also found that a floating well structure used for CMOS does not protect MOSFETs from plasma damage.

Design methodology for low power, high-speed CMOS devices utilizing SOI technology

We have compared CMOS gate performances between bulk and SOI structures, using the circuit simulator SPICE with the simplest assumptions. Main results are as follows: (1) We have demonstrated that it is possible to estimate CMOS/SOI performances using the circuit simulator SPICE without any specific physical models for SOI transistors. (2) The reduction effect of the drain parasitic capacitance by the CMOS/SOI technology becomes more remarkable with a decrease in the supply voltage. (3) Just by increasing the channel width of the CMOS/SOI keeping its power consumption equal to that of the CMOS/BULK, the propagation delay time dependence on large load capacitance can be improved dramatically with higher drivability.<<ETX>>