Natsuki Yokoyama

Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate

Chemical-mechanical-polishing (CMP) was used to smooth the surface of a SiGe substrate, on which strained-Si n- and p-MOSFETs were fabricated. By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, namely, to 0.4 nm (rms). A strained-Si layer was then successfully grown on the CMP-treated SiGe substrate. The fabricated strained-Si MOSFETs showed good turn-off characteristics, (i.e., equivalent to those of Si control devices). Moreover, capacitance-voltage (CV) measurements revealed that the quality of the gate oxide of the strained-Si devices was the same as that of the Si control devices. Flat-band and threshold voltages of the strained-Si devices were different from those of the Si control devices mainly due to band discontinuity. Electron and hole mobilities of strained-Si MOSFETs under a vertical field up to 1.5 MV/cm increased by 120% and 42%, respectively, compared to the universal mobility. Furthermore, current drive of the n- and p-MOSFETs (L/sub eff//spl ges/0.3 /spl mu/m) was increased roughly by 70% and 50%, respectively. These improvements in characteristics indicate that CMP of the SiGe substrate is a critical technique for developing high-performance strained-Si CMOS.

Process and device technologies for 1 Gbit dynamic random‐access memory cells

This article discusses the technological issues involved with continuing the miniaturization of dynamic random‐access memory cells into the gigabit era. Ever‐smaller giga‐generation dynamic random‐access memory cells require three‐dimensional high‐charge density capacitors with high‐e insulating films, leading to the need for further improvements in lithographic resolution for ever‐smaller, higher aspect ratio memory cells, and planarization technologies for reducing the memory‐cell height. This article demonstrates two technologies for meeting these two requirements: high acceleration energy electron‐beam lithography and KrF excimer‐laser phase‐shift photolithography, and plate‐wiring merge technology. Metal–insulator–metal 1.6 nm Ta2O5 CROWN capacitors and single Si3N4 spacer OSELO isolation technology for an experimental 1 Gbit dynamic random‐access memory chip are also discussed.

Process and properties of Pt/Pb(Zr, Ti)O3/Pt integrated ferroelectric capacitors

Abstract A one-mask-patterned ferroelectric capacitor memory cell structures designed with a 0.5-μm feature size were fabricated. Oxygen plasma treatment after dry etching decreased the leakage current to as low as as-deposited film. The one-mask-patterned ferroelectric capacitors with switching charge almost equal to as-deposited film were achieved. Ferroelectric memories as dense as dynamic random access memories will become possible with this technology.

Normally-off SiC-JFET inverter with low-voltage control and a high-speed drive circuit

A highly efficient inverter was achieved by using normally-off SiC-JFETs (silicon carbide junction FETs) as switching devices. A precise control system for the gate voltage and the high-speed driver circuit are quite important issues in the realization of an inverter system for operating JFETs with threshold voltage lower than 2V and for the reduction of switching loss. A two step push-pull circuit for precise control of the gate voltage and a speed-up capacitor circuit for high-speed operation are developed and high-speed switching of 600 V/2A SiC-JFET modules is demonstrated. The 50 W fan motor for an exterior unit of an air conditioner has been successfully operated by these SiC modules and developed driver circuits, and the the inverter efficiency was improved by about 6%, compared with conventional IGBT inverters.

A 7.03-/spl mu/m/sup 2/ Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching

A ferroelectric memory cell with an area of only 7.03 /spl mu/m/sup 2/ designed with a 0.5-/spl mu/m rule has been fabricated. It performs Vcc/2-plate nonvolatile DRAM operation: ordinary DRAM operation and automatic nonvolatile writing when Vcc is shut down. A non-separated plate electrode and a capacitor patterned by one-mask dry etching reduce cell area. Planarization of the poly-Si plugs and the use of H-less metallization/passivation processes retain the PZT capacitor characteristics (Pr=50 fC/bit) and achieves ferroelectric write/read under /spl plusmn/2.5-V operation in 4-K bit memory cell arrays.

Enhanced performance of strained Strained-Si MOSFETs on CMP sige virtual substrate

Strained-Si n- and p-MOSFETs have been fabricated on a chemical-mechanical planarized (CMP) SiGe virtual substrate (VS). By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, to 0.4 nm (rms). Large increases in mobility, of 120% and 42%, were obtained for electrons and holes, respectively, over the universal mobility at a vertical field of ~1.5 MV/cm. Improvements in current drive of 70% and 51% were also observed for n- and p- MOSFETs (Leff = 0.24 μm), respectively. These results indicate that the planarization of the SiGe VS is a critical technology for developing high-performance strained-Si CMOS.

Normally-Off 4H-SiC Vertical JFET with Large Current Density

We developed normally-off 4H-SiC vertical junction field effect transistors (JFETs) with large current density. The effect of forming an abrupt junction between the gate and the channel was simulated, and vertical JFETs were then fabricated with abrupt junctions. As a result, a large rated drain current density (500 A/cm2) and a low specific on-resistance (2.0 mWcm2) were achieved for small devices. The blocking voltage was 600 V. These results were due to a reduction of the threshold voltage by forming the abrupt junction between the gate and the channel.

A 0.29-/spl mu/m/sup 2/ MIM-CROWN cell and process technologies for 1-gigabit DRAMs

In keeping with the trend of reducing DRAM cell area, with a target for 1-gigabit DRAMs of less than 0.3 /spl mu/m/sup 2/, the authors have developed a 0.29-/spl mu/m/sup 2/ metal/insulator/metal crown-shaped capacitor (MIM-CROWN) cell with low height by using 0.16-/spl mu/m process technologies.<<ETX>>

Influence of Lateral Spreading of Implanted Aluminum Ions and Implantation-Induced Defects on Forward Current–Voltage Characteristics of 4H-SiC Junction Barrier Schottky Diodes

Forward current density (J_F)-forward voltage (V_F) characteristics are experimentally and computationally investigated for 4H-silicon carbide junction barrier Schottky (JBS) diodes with a lightly doped (3 - 5 times10¹⁵ cm^-3) drift layer and 2-mum-wide p⁺ stripe regions separated by 1 mum. The J_F-V_F characteristics of fabricated JBS diodes are compared with those of Schottky barrier diodes simultaneously fabricated on the same epitaxial wafers. These J_F-V_F characteristics are also compared with those of simulated JBS diodes, assuming boxlike and Monte Carlo-simulated profiles of aluminum. In the simulation of aluminum ion implantation, concentration contours of created interstitials and vacancies are calculated, and their influence on the J_F-V_F characteristics of JBS diodes is discussed in terms of degradation of electron mobility in the surface region of the drift layer.

Fully CMOS compatible on-LSI capacitive pressure sensor fabricated using standard back-end-of-line processes

A surface micromachined capacitive pressure sensor was fabricated using conventional back-end of line (BEOL) processes in a standard CMOS fabrication line. The combination of standard interlayer dielectric and tungsten was used as sacrificial layers and electrodes, which achieves a large etching selectivity in sacrificial layer removal processes. Measured dependences of capacitance on applied pressure showed a good agreement with simulated results. Although the sensor used metal and amorphous layers in the moving parts (diaphragm), it showed excellent reliability. Sensor characteristics did not change after the deflection test for more than 50M times, temperature cycling test (-55 to 150 deg C, 500 cycles, JEDEC standard) and humidity test (85 deg C, 85% for 100 hr). The process enables us to monolithically integrate MEMS structures with the most advanced CMOS integrated circuits because they use only low temperature processes. Integrating MEMS with high performance digital circuits such as MPU as well as analog circuits enables ultra-tiny one-chip sensor devices.