Yun Young Yeoh

Investigation of nanowire size dependency on TSNWFET

Nanowire size (dNW) dependency of various electrical characteristics on gate all around twin silicon nanowire MOSFET (TSNWFET) is investigated to understand overall performance of nanowire transistor deeply. When dNW decreases, current drivability (Ion) normalized by circumference at the same VG-VTH improves and maximizes at dNW of 4 nm. And mobility is also estimated with capacitance and series resistance. All the experimental investigation shows that dNW of 4 nm is the best point to maximize the volume inversion effect on gate all around nanowire MOSFET.

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

Gate-all-around twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on bulk Si wafer is successfully fabricated to achieve extremely high drive currents of 2.37 mA/mum for n-channel and 1.30 mA/mum for p-channel TSNWFETs with mid-gap TiN metal gate. It also shows good short channel effects immunity down to 30 nm gate length due to GAA structure and nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.

Observation of Single Electron Tunneling and Ballistic Transport in Twin Silicon Nanowire MOSFETs (TSNWFETs) Fabricated by Top-Down CMOS Process

the authors report transport experiments on gate-all-around (GAA) TSNWFETs fabricated by top-down CMOS processes. The nanowire with 45 nm gate length exhibits single electron tunneling, and the total capacitance extracted from the measured data is in good agreement with the self-capacitance of an ideal cylinder. The nanowire with 125 nm gate length shows conductance quantization suggesting ballistic transport. The temperature dependence of the conductance steps is consistent with the crossover from classical to ballistic

Temperature-Dependent Characteristics of Cylindrical Gate-All-Around Twin Silicon Nanowire MOSFETs (TSNWFETs)

The characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with a radius of 5 nm have been measured in temperatures T ranging from 4 to 300 K. The dependence of the off-current suggests that thermal generation in the channel is the main leakage mechanism. The dependence of the subthreshold swing exhibits no body effects but shows degradations due to slight differences in the threshold voltages and in the body effect constants of the twin nanowires. The T dependence of the peak normalized transconductance gm /VDS gives a clue of 1-D phonon scattering and suggests that surface roughness scattering at the nanowire wall is dominant at low values.

Gate-all-around Twin Silicon nanowire SONOS Memory

We have developed gate-all-around (GAA) SONOS with ultra thin twin silicon nanowires for the first time. By using channel hot electron injection (CHEI) and hot hole injection (HHI) mechanisms, program speed of 1 mus at V_d = 2 V, V_g = 6 V and erase speed of 1 ms at V_d = 4.5 V, V_g = -6 V are achieved with 2~3 nm nanowire and 30 nm gate. Nanowire size below 10 nm dependencies on V_th shift (DeltaV_th) and the program/erase (P/E) characteristics are investigated. As nanowire diameter (d_nw) decreases, faster program speed and larger DeltaV_th are observed.

TSNWFET for SRAM cell application: Performance variation and process dependency

ION is increased about 25 % with the width/height (W/H) of 12/24 nm nanowire (NW) in comparison with the W/H of 12/12 nm at VG-VTH = 1 V. With these results, we have successfully fabricated NW SRAM arrays with the W/H of 5/15 nm and LG of 40 nm for the first time. Static noise margin (SNM) of 325 mV is achieved at VD = 1 V. NW height and gate oxide thickness dependency of n-ch twin silicon nanowire MOSFET (TSNWFET) on device variations is investigated. Line edge roughness and size variation are more critical than random dopant fluctuation in TSNWFET.

Characterization and Modeling of 1/

In this paper, the volume trap densities Nt are extracted from gate-all-around silicone-nanowire FETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting Nt, the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Finally, radius dependence of the cylindrical 1/f model developed is discussed.

f

Strained silicon nanowire transistor with embedded SiGe (e-SG) source/drain is investigated for the first time on experiments. By compressive stress induced by e-SG, PMOS performance is improved by about 85%. <110>-oriented nanowire channel also contributes 80% PMOS performance improvement relative to <100> direction. By combination of uniaxial stress and <110> channel direction, up to 136% PMOS performance enhancement is obtained so that superior PMOSFET to NMOSFET is for the first time observed with silicon channel material.

Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

The series resistance, R sd in silicon nanowire FETs (Si-NWFET) is extracted unambiguously, using the Y -function technique, in conjunction with the drain current and transconductance data. The volume channel inversion in Si-NWFET renders the charge carriers relatively free of the surface scattering and concomitant degradation of mobility. As a result, the Y -function of Si-NWFET is shown to exhibit a linear behavior in strong inversion, thereby enabling accurate extraction of R sd. The technique is applied to nanowire devices with channel lengths 82, 86, 96, 106, 132, and 164 nm, respectively. The extracted R sd values are shown nearly flat with respect to the gate voltage, as expected from Ohmic contacts but showed a large variation for all channel lengths examined. This indicates the process parameters involved in the formation of series contacts vary considerably from device to device. The present method only requires a single device for extraction of R sd and the iteration procedure for data fitting is fast and stable.

Experimental Investigation on Superior PMOS Performance of Uniaxial Strained ≪110≫ Silicon Nanowire Channel By Embedded SiGe Source/Drain

Presented in this letter are the C-V data, measured from nanowire capacitors, which have been fabricated by connecting in parallel a large number of identically processed nanowire FETs. The C-V curves were examined over a range from accumulation to inversion with varying frequencies and at different electrode configurations. The gate response of the undoped and floating channel is investigated using C-V data, and the inversion charge and carrier mobility are accurately extracted by eliminating the effects of parasitic capacitances and series resistance Rsd. These observed data are compared with the data from planar MOS capacitor.