Yung-Feng Chen

Gate-alloy-related kink effect for metamorphic high-electron-mobility transistors

Gate-metal-related kink effects in InAlAs∕InGaAs∕GaAs metamorphic high-electron-mobility transistors have been investigated. Improvements on the kink effect have been observed by using the higher Schottky barrier height gate alloys, including Ti∕Au, Ni∕Au, and Pt∕Au, as compared to the use of the conventional Au gate metal. In comparison with gate alloy combinations, the devices with Ti∕Au alloy exhibit superior noise characteristics, whereas those with Ni∕Au alloy demonstrate the highest power characteristics. With the gate dimensions of 1.2×200μm2, the device minimum noise figure, NFmin, is 1.17dB at 2.4GHz by using Ti∕Au and the output power is 13.14dBm at 2.4GHz by using Ni∕Au. Significant rf characteristics have also been improved upon that with Au gate.

Nanoepitaxy of GaAs on a Si(001) substrate using a round-hole nanopatterned SiO2 mask

GaAs is grown by metal-organic vapor-phase epitaxy on a 55 nm round-hole patterned Si substrate with SiO(2) as a mask. The threading dislocations, which are stacked on the lowest energy facet plane, move along the SiO(2) walls, reducing the number of dislocations. The etching pit density of GaAs on the 55 nm round-hole patterned Si substrate is about 3.3 × 10(5) cm(-2). Compared with the full width at half maximum measurement from x-ray diffraction and photoluminescence spectra of GaAs on a planar Si(001) substrate, those of GaAs on the 55 nm round-hole patterned Si substrate are reduced by 39.6 and 31.4%, respectively. The improvement in material quality is verified by transmission electron microscopy, field-emission scanning electron microscopy, Hall measurements, Raman spectroscopy, photoluminescence, and x-ray diffraction studies.

Nano epitaxial growth of GaAs on Si (001)

Nano epitaxial growth (NEG) is used to develop GaAs monolithic hetero-epitaxy onto Si (001). For the GaAs grown in a nanopatterned trench with an aspect ratio of 5, the dislocations originally generated at the GaAs/Si interface are mostly isolated by the SiO2 sidewall. Compared with the conventional-planar Si substrate, implementing the NEG technique is able to decrease the dislocation density from about 109 cm−2 to almost zero. It is also confirmed that NEG is capable of confining the dislocations within the GaAs initial epitaxial layer (<100 nm), which meets the requirement of relatively less complicated epitaxial processes.

Heteroepitaxy for GaAs on Nanopatterned Si (001)

An almost defect pit-free GaAs is achieved using nanopatterned Si (001). The largest nanopattern with an aspect ratio of 4.18 and the narrowest strip of around 55 nm in width are adopted in this letter. The threading dislocations, beginning from the GaAs-Si interface and moving along the facet plane to the sidewall, are interrupted within the initial epitaxial layer. With the aspect ratio increasing from 0.44 to 2.04, the etching defect pit density can be decreased from around 5.0 × 109 cm-2 to almost zero. The improvement in material quality is verified by transmission electron microscopy, photoluminescence, and X-ray diffraction studies.

Quality Improvement of GaN on Si Substrate for Ultraviolet Photodetector Application

GaN is grown on an Si substrate using metal-organic vapor-phase epitaxy. Compared with the full width at half maximum values from X-ray diffraction patterns and photoluminescence spectra of conventional GaN on the Si substrate, those of GaN on the Si substrate with the insertion of various-temperature AlN nucleation layers and Al0.3Ga0.7N/GaN superlattice intermediate layers are reduced by 34.9% and 25.6%, respectively. In addition, Raman spectra show that residual stress on the GaN epilayers decreased by 0.35 GPa. The c-lattice parameter of the GaN epilayer is 5.1844 Å, which is close to that of an unstrained GaN layer. Ultraviolet metal-semiconductor-metal photodetectors are fabricated on an almost-crack-free GaN surface. The dark current of a photodetector on the Si substrate is 2.4 ×10-11 A at a 9 V applied bias, which is one order of magnitude smaller than that of a photodetector on a conventional sapphire substrate. The maximum quantum efficiency value of a photodetector on the Si substrate is ~ 97% with an incident light wavelength of 360 nm and a 9 V applied bias.

Dislocation reduction of InAs nanofins prepared on Si substrate using metal-organic vapor-phase epitaxy

InAs nanofins were prepared on a nanopatterned Si (001) substrate by metal-organic vapor-phase epitaxy. The threading dislocations, stacked on the lowest-energy-facet plane {111}, move along the SiO2 walls, resulting in a dislocation reduction, as confirmed by transmission electron microscopy. The dislocations were trapped within a thin InAs epilayer. The obtained 90-nm-wide InAs nanofins with an almost etching-pit-free surface do not require complex intermediate-layer epitaxial growth processes and large thickness typically required for conventional epitaxial growth.

Improvement of defect reduction in semi-polar GaN grown on shallow-trenched Si(001) substrate

The improved design of sub-micron trenches on Si(001) substrate was demonstrated for defect suppression in semi-polar selectively-grown GaN layers. Cathodoluminescence and transmission electron microscopy measurements revealed a dramatically decreased density of threading dislocations and stacking faults near the surface of the overgrown GaN layer when the trench width ranged from 500 to 1500 nm. It was observed that defects were effectively trapped inside the trench when the ratio of trench depth to the SiO2 thickness is less than 0.66. In addition, a significant reduction of intrinsic polarization electric field was achieved for the InGaN/GaN multiple quantum well on the GaN selectively grown from the Si trenches.

Cathodoluminescence studies of GaAs nano-wires grown on shallow-trench-patterned Si

The optical properties of GaAs nano-wires grown on shallow-trench-patterned Si(001) substrates were investigated by cathodoluminescence. The results showed that when the trench width ranges from 80 to 100 nm, the emission efficiency of GaAs can be enhanced and is stronger than that of a homogeneously grown epilayer. The suppression of non-radiative centers is attributed to the trapping of both threading dislocations and planar defects at the trench sidewalls. This approach demonstrates the feasibility of growing nano-scaled GaAs-based optoelectronic devices on Si substrates.

Influence of polysilicon thickness on the microwave attenuation losses of the CPWs fabricated on polysilicon-passivated high-resistivity silicon substrates

In recent years, a high resistivity silicon (HR-Si) substrate is of interest as a substrate upon which integrated radio-frequency (RF) and millimeter wave circuits can be realized. Because the material have an inherent defect density, surface effect and resistivity degradation near the interface between an insulating oxide and a HR-Si substrate tend to overshadow the potentially low RF loss levels in HR-Si substrate. Fixed positive charges within the oxide attract free carriers near the substrate surface, leading to an accumulation or inversion layer on the silicon surface. Consequently, these free carriers act as the thin surface-channel at the Si/oxide interface, thus reducing the resistivity of the silicon surface and increasing the substrate loss. In fact, several surface passivation approaches have been used to overcome these shortcomings. For example, local resistivity can be enhanced by high-dose implantation (e.g, argon) to convert LR-Si substrate to HR-Si substrate [1], or a trap-rich passivation layer (e.g., polysilicon or amorphous silicon) between the oxide layer and the HR-Si substrate to prevent the carrier accumulation [2]. Polysilicon films deposited by LPCVD are the most widely used as a surface passivation layer on on HR-Si substrate and a thickness between 300nm and 400 nm were generally used. For HR-Si surface passivation application, the properties of LPCVD-deposited polysilicon (or amorphous silicon) are known to be significantly dependent on deposition conditions and annealing conditions [3].

Optical Studies of GaAs Nanowires Grown on Trenched Si(001) Substrate by Cathodoluminescence

The strains in GaAs nanowires, which were grown from 1700- to 80-nm-wide trenches on the Si(001) wafer with SiO2 masks, were investigated by cathodoluminescence. For 1700- to 500-nm-wide trenches, the in-plane tensile strain at 15 K decreases with the decreasing trench width. The strain increases abruptly when the trench width is 300 nm, and then decreases as the trench width is further decreased. The results revealed that the stress induced by the SiO2 sidewalls dominates when the width is less than the depth of the trench. This approach provides an effective technique to measure the strain of a single nanowire and helps for the demonstration of selectively-grown GaAs with a designed strain.