Yung-Huei Lee

Prediction of Logic Product Failure Due To Thin-Gate Oxide Breakdown

Gate oxide breakdown is a key mechanism limiting IC lifetime. Breakdown is typically characterized on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This work compares the predictions of capacitor-based models to results from accelerated lifetest of logic CPU products. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that an important factor was the different sensitivities of logic circuits vs. cache cells and of n and p transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data including these effects. Once a model is validated, the paper discusses how it can be used to assess the reliability impact of changes in processing, use conditions, and circuit design

RTS Noise Characterization in Flash Cells

A method is presented for using noise spectroscopy to efficiently characterize random telegraph signal (RTS) in flash cells, in particular allowing the determination of oxide depth of the traps from the gate voltage dependence of the frequency spectrum of the trap. The RTS traps are not uniformly distributed in nitrided oxides, and increased nitridation of the tunneling oxide results in larger RTS specifically because of the proximity of the additional nitrogen to the substrate. The various effects of program/erase cycling on individual RTS related traps are qualitatively analyzed.

The impact of PMOST bias-temperature degradation on logic circuit reliability performance

This work investigated the impact of pMOST bias-temperature (BT) degradation on logic products speed (Fmax) and minimum allowed operating voltage (Vccmin). BT degradation occurs during the product Burn-In and under the normal circuit operation. The interaction of device degradation and circuit performance is explained. Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanism and degradation models are proposed to explain the interaction of fluorine with device and circuit reliability. Process optimization, such as fluorine implant, can be used to reduce the pMOST BT impact on circuit degradation. Reliability guardband in Fmax and Vccmin is recommended, as part of the production testing to ensure reliable logic product performance and functionality during the products lifetime. A guardband methodology is also discussed in the paper.

Drain Read Disturb Assessment of NOR Flash Memory

Drain read disturb (RD) is becoming an intrinsic reliability concern for NOR flash scaling and MLC operation. A drain RD time-to-error model has been generated which takes into consideration the voltage dependence, read cycling, and Poisson random statistics. This model can be used to optimize the circuit read timing design and to assess process improvement to ensure that products meet the customer spec and lifetime usage.

Thin-Gate-Oxide Breakdown and CPU Failure-Rate Estimation

Gate-oxide breakdown is a key mechanism limiting IC lifetime. Lifetime is typically extrapolated from accelerated tests on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This paper details a capacitor-based model and compares the predictions of the model to results from accelerated lifetest of actual logic CPU products, discussing the assumptions which make such a comparison necessary. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that important factors included the different sensitivities of logic circuits versus cache cells and of and transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data, including these effects. Once a model is validated, this paper discusses how it can be used to assess the reliability impact of changes in silicon processing and product use conditions.

The Role of Shallow Trench Isolation on Channel Width Noise Scaling for Narrow Width CMOS and Flash Cells

RTS noise is a growing issue in flash memory as the cell size scales down. By investigating NMOS and Ring devices, it is shown that noise induced by the STI edge dominates cell RTS/noise with scaling or after cycling. Device 1/f characterization highlights the drain STI edge as a critical area for RTS improvement in flash.

Managing Bias-Temperature Instability for Product Reliability

A NBTI model has been generated which takes into consideration AC recovery. This model can be used to improve the connection between the DC stress measurements of a discrete device and AC product usage in a real device. The model can be incorporated into circuit aging simulations to check the NBTI degradation for a simple circuit. For complicated circuitry such as CPU, NBTI degradation should be managed through process optimization, circuit timing design, and product test guardband to ensure that products meet customer spec and lifetime usage.

Robust Inductor Design for RF Circuits

Design of monolithic spiral inductors with electromigration (EM) robustness has been demonstrated. By adding small metal reservoir structures in the underpass area, inductor EM lifetime can be significantly improved. Measurements showed that the metal reservoir structures do not have an impact on inductor Q and inductance. Adding these structures hence allows more aggressive and scalable RF IC design

RTS and 1/f Noise in Flash Memory

This work investigates the RTS noise in Flash memory from the perspective of a single cell. In this study, RTS noise in a cell is measured in the frequency domain instead of time domain to increase the efficient identification of individual RTS traps over a broader range of trap lifetime, from seconds to mus in comparison to the conventional time domain approach which typically identifies traps with ms lifetimes at shortest. By converting the frequency domain parameters back to their time domain counterparts, the trap location in the tunneling oxide can be characterized. This work also revisits the relationship between RTS and 1/f noise of flash cells and investigates the change of RTS noise after P/E cycling.

Effect of trench edge on pMOSFET reliability

Abstract Scaling of MOSFET increases the portion of the device channel that is affected by proximity to the shallow trench isolation (STI) trench. Experimental data show that this proximity effect results in a channel-width dependent hot-carrier degradation of pMOSFETs in a 0.25 μm CMOS technology. Device simulations are used to show that electric field differences between the STI edge and center channel region are responsible for the channel-width dependent degradation. Discrete device measurements and product burn-in data are presented to support this explanation of the pMOSFET degradation mechanism.