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Dive into the research topics where M. Agostinelli is active.

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Featured researches published by M. Agostinelli.


international reliability physics symposium | 2008

BTI reliability of 45 nm high-K + metal-gate process technology

Sangwoo Pae; M. Agostinelli; M. Brazier; Robert S. Chau; G. Dewey; Tahir Ghani; M. Hattendorf; J. Hicks; Jack T. Kavalieros; K. Kuhn; M. Kuhn; Jose Maiz; Matthew V. Metz; K. Mistry; C. Prasad; S. Ramey; A. Roskowski; J. Sandford; C. Thomas; J. Thomas; C. Wiegand; J. Wiedemer

In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.


international reliability physics symposium | 2006

Prediction of Logic Product Failure Due To Thin-Gate Oxide Breakdown

Yung-Huei Lee; Neal Mielke; M. Agostinelli; Sukirti Gupta; Ryan Lu; William McMahon

Gate oxide breakdown is a key mechanism limiting IC lifetime. Breakdown is typically characterized on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This work compares the predictions of capacitor-based models to results from accelerated lifetest of logic CPU products. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that an important factor was the different sensitivities of logic circuits vs. cache cells and of n and p transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data including these effects. Once a model is validated, the paper discusses how it can be used to assess the reliability impact of changes in processing, use conditions, and circuit design


international reliability physics symposium | 2005

Random charge effects for PMOS NBTI in ultra-small gate area devices

M. Agostinelli; Sangwoo Pae; W. Yang; C. Prasad; D. Kencke; S. Ramey; E. Snyder; S. Kashyap; M. Jones

PMOS transistor degradation due to negative bias temperature instability (NBTI) has been shown to be a major transistor reliability mechanism. The effect of PMOS NBTI on the minimum operating voltage of a cache cell (Vmin) has been recently demonstrated, and the modeling of the degradation of ultra small gate area devices is vital for the accurate modeling of Vmin. Recent data and simulation has indicated that random fluctuations in device degradation are present under stress. This paper examines the source of these random fluctuations in device degradation due to PMOS NBTI.


international reliability physics symposium | 2009

Frequency and recovery effects in high-κ BTI degradation

S. Ramey; C. Prasad; M. Agostinelli; Sangwoo Pae; Steven V. Walstra; Satrajit Gupta; J. Hicks

Net end-of-life aging prediction under realistic use conditions is the key objective for any product aging model. In this paper, a net degradation model is introduced and effects such as recovery, subsequent degradation, frequency, duty cycle, and recovery bias are evaluated. The high-κ recovery behavior observed is consistent with SiO2 gate stacks, which allows the use of SiO2 models to predict recovery in both NMOS and PMOS high-κ transistors.


international reliability physics symposium | 2013

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

C. Prasad; Lei Jiang; D. Singh; M. Agostinelli; C. Auth; P. Bai; T. Eiles; J. Hicks; Chia-Hong Jan; K. Mistry; S. Natarajan; B. Niu; P. Packan; Daniel Pantuso; I. Post; S. Ramey; Anthony Schmitz; B. Sell; S. Suthram; J. Thomas; C. Tsai; P. Vandervoorn

This paper describes various measurements on self-heat performed on Intels 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.


international reliability physics symposium | 2014

Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures

C. Prasad; M. Agostinelli; J. Hicks; S. Ramey; C. Auth; K. Mistry; S. Natarajan; P. Packan; I. Post; S. Bodapati; M. Giles; Sukirti Gupta; S. Mudanai; K. Kuhn

A summary of NBTI variation is reported on large data-sets across five generations of Intel technologies (90 nm to 22 nm) and a comparison of statistical frameworks is utilized to show the universality of variation metrics across generations. Large volumes of data and modeling are emphasized as critical to enable accurate simulations of NBTI in extreme tails.


international reliability physics symposium | 2008

Dielectric breakdown in a 45 nm high-k/metal gate process technology

C. Prasad; M. Agostinelli; C. Auth; M. Brazier; Robert S. Chau; G. Dewey; Tahir Ghani; M. Hattendorf; J. Hicks; J. Jopling; Jack T. Kavalieros; R. Kotlyar; M. Kuhn; K. Kuhn; Jose Maiz; B. McIntyre; Matthew V. Metz; K. Mistry; Sangwoo Pae; W. Rachmady; S. Ramey; A. Roskowski; J. Sandford; C. Thomas; C. Wiegand; J. Wiedemer

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.


international reliability physics symposium | 2015

Transistor aging and reliability in 14nm tri-gate technology

S. Novak; C. Parker; D. Becher; Mark Y. Liu; M. Agostinelli; M. Chahal; P. Packan; P. Nayak; S. Ramey; S. Natarajan

This paper details the transistor aging and gate oxide reliability of Intels 14nm process technology. This technology introduces Intels 2nd generation tri-gate transistor and the 4th generation of high-κ dielectrics and metal-gate electrodes. The reliability metrics reported here highlight reliability gains attained through transistor optimizations as well as intrinsic challenges from device scaling.


Microelectronics Reliability | 2006

PMOS NBTI-induced circuit mismatch in advanced technologies

M. Agostinelli; S. Lau; Sangwoo Pae; P. Marzolf; H. Muthali; S. Jacobs

PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be a significant concern to present CMOS technologies. This is of particular concern for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS NBTI induced mismatch on analog circuits in a 90nm technology.


international reliability physics symposium | 2011

Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2 nd generation high-k/metal gate transistors

Anisur Rahman; M. Agostinelli; P. Bai; G. Curello; H. Deshpande; Walid M. Hafez; Chia-Hong Jan; K. Komeyli; Joodong Park; K. Phoa; C. Tsai; J.-Y. Yeh; Jessica Xu

Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the Logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors are studied and excellent reliability is demonstrated. Importance of process optimizations to integrate robust I/O transistors without degrading performance and reliability of Logic transistors emphasized. Finally, Intrinsic and defect reliability monitoring for HVM are addressed.

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