Yuning Zhao

A learnable parallel processing architecture towards unity of memory and computing.

Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named “iMemComp”, where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped “iMemComp” with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on “iMemComp” can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

The impact of line edge roughness on the stability of a FinFET SRAM

3D mixed-mode device-circuit simulation is presented to investigate the impact of line edge roughness (LER) on the stability of a FinFET SRAM. In this work, LER sequence is statistically generated by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The sensitivity of 20 nm FinFET SRAM of Read and Write static noise margins (SNM) to fin LER is evaluated. The results show that FinFET SRAM is more tolerant of disturbance in write operation than in read disturbance. The dependence of Read SNM on fin LERs root mean square (RMS) amplitude, fin thickness and supply voltage is also analyzed. Furthermore, methods to reduce the LER effect on the FinFET SRAMs read stability are introduced. Optimization of the cell ratio by a multiple-fin design, control of the access transistors gate bias voltage and replacement of a 6T cell with an 8T cell are possible solutions to continue the scaling trend of SRAM in the nanoscale CMOS technology.

Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect Transistors

The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high-V gs region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.

3-D simulation of geometrical variations impact on nanoscale FinFETs

Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness (LER) and oxide thickness fluctuations (OTF). A full 3-D statistical simulation is presented to investigate the impact of geometrical variations on the FinFETs performance. In this work, roughness is introduced by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The influence of different geometrical variation sources is compared and summarized. The results shows that FinFETs performance is most sensitive to the fin LER, which causes a remarkable shift and fluctuations in threshold voltage, drain induced barrier lower effect (DIBL) and leakage current. The impact of gate LER follows that of fin LER. The simulation also suggests quantum confinement effect accounts for the aggressive fluctuations due to fin LER.

Effects of Shell Strain on Valence Band Structure and Transport Properties of Ge/Si1-xGex Core-Shell Nanowire

Various Si1-xGex shell strains induced by changing the thickness or tuning the Ge and Si contents as well as by modulating the valence band structure and hole transport characteristics of core/shell nanowire field effect transistors (FETs) have been calculated. As Si1-xGex shell thickness increases, the strained valence subbands shift upwards and warp markedly. Most of the corresponding hole effective masses of the top five subbands decrease. Meanwhile, the hole mobility of the Ge(110) nanowire increases with increasing shell thickness. As the Ge concentration in the Si1-xGex shell decreases, the strained valence subbands and hole mobility show similar shifts. As a result, our calculation indicates the possibility of improving the nanowire performance of heterostructure nanowire FETs.

Performance Evaluation of GaAs–GaP Core–Shell-Nanowire Field-Effect Transistors

We evaluate the performance of GaAs-GaP core-shell (C-S)-nanowire (NW) field-effect transistors by employing a semiclassical ballistic transport model. The valence-band structures of GaAs-GaP C-S NWs are calculated by using a kldrp method including the strain effect. The calculations show that the strain causes substantial band warping and pushes valence subbands to move up. We demonstrate that the on current can be enhanced with the strength of strain induced in the core, but an extremely thin equivalent oxide thickness may suppress the effect of the strain-induced current improvement. The achieved results can provide a design guide for optimizing device performance.

Atomic Monte-Carlo simulation for CBRAM with various filament geometries

An atomic Monte-Carlo simulator of Conductive Bridge Random Access Memory (CBRAM) is developed to investigate the microscopic properties of filament growth and dissolution during Forming/SET and RESET processes. The cluster growth during nucleation correlated with electrochemical reactions and cations transportation are included. The impacts of the critical material parameters on the geometry of conductive filaments (CF) are clarified by the simulator. The conical and dendrite shape CF experimentally observed by different groups are simulated by tuning the critical material parameters. Using the simulator, the microscopic properties of Forming/SET and RESET processes with different CF geometries are investigated and the retention behaviors can be analyzed.

Insights into resistive switching characteristics of TaO x -RRAM by Monte-Carlo simulation

An atomistic Monte-Carlo simulator is developed for TaO_x-based resistive switching random access memory (RRAM) including both the generation & recombination effect of oxygen vacancy defects with oxygen ions and the phase change effect between Ta₂O₅ and TaO₂. Using the developed simulation tool, the resistive switching characteristics of the bi-layered Ta₂O₅/TaO_x RRAM are investigated. The typical self-compliance behavior measured in the bi-layered Ta₂O₅/TaO_x RRAM is reproduced by considering the interaction between Ta₂O₅ and TaO_x, indicating that TaO_x layer plays a critical role to the self-compliance behavior.

Variability Induced by Line Edge Roughness in Double-Gate Dopant-Segregated Schottky MOSFETs

Intrinsic parameter fluctuations introduced by process variations, such as line edge roughness (LER), create an increasing challenge to the CMOS technology scaling. In this paper, variations in double-gate dopant-segregate Schottky (DSS) MOSFETs, caused by LER of silicon-fin, are systematically investigated using statistical technology computer-aided design simulations. The impact of LER on both Schottky barrier and DSS-MOSFETs are examined contrastively. The results show that DSS-MOSFETs offer a larger and more uniform drive current, but suffer a more serious Vt fluctuation. The cause of such larger Vt flutuation is also analyzed, thus providing a good starting point to propose way to solve this problem.

Triple-gate FinFETs with Fin-thickness Optimization to Reduce the Impact of Fin Line Edge Roughness

Shimeng Yu, Yuning Zhao, Gang Du, Jinfeng Kang, Ruqi Han, and Xiaoyan Liu* Institute of Microelectronics, Peking University, Beijing 100871, P. R. China Shenzhen Graduate School, Peking University, Guangdong 518055, P. R. China *xyliu@ime.pku.edu.cn Introduction: Intra-die fluctuations in the nanoscale CMOS technology emerge due to intrinsic parameter fluctuations induced by line edge roughness (LER) [1]. LER can cause the random deviation of the line edge from its ideal pattern and it does not reduce with scaling down of line width [2]. FinFET is a promising candidate that can be applied into sub-30nm technology with good ability to suppress the short channel effects (SCEs) [3]. However, to reduce fluctuations of FinFETs performance is still imperative [4] and the strongest fluctuations are introduced by the fin LER [5]. As the fin is conventionally designed less than one third of the channel length to suppress SCEs [6], it imposes a big challenge on the lithography and etching. Here we propose to relax the fin-thickness constraints in order to reduce the influence of intra-die fluctuations. Through our 3-D simulation, we suggest using triple-gate FinFETs with optimized fin-thickness to minimize the fin LER effects, meanwhile to suppress SCEs under a tolerable degree. Device Structure and Simulation Method: Fig. 1 shows the device structure of triple-gate FinFETs with fin LER. The geometrical and doping parameters used in simulation are listed in Table 1. Fin roughness is generated by a Fourier analysis of the Gaussian autocorrelation function introduced in our earlier work [7]. Fig. 2 is schematic of the flow to generate the random sequence. The properties of FinFETs we consider include threshold voltage Vt,lin at Vds=50mV and Vt,sat at Vds=1V; the value of the drain induced barrier lower effect (DIBL) defined as (Vt,lin-Vt,sat)/ Vds; drive current Ion and leakage current Ioff. Hundreds of 20nm double-gate (DG) and triple-gate (TG) FinFETs with different fin-thickness (Tsi) are simulated in 3-D by ISE-TCAD tools [8]. Since LER does not reduce with scaling down of line width [2], we assume all the samples have the same rms amplitude (1nm) of fin LER in spite of different Tsi. Fisrtly, FinFETs with smooth line edge (referred as ideal) are evaluated. Then FinFETs with fin LER (referred as rough) are simulated to investigate their properties’ shifts (evaluated by average value Avg) and fluctuations (evaluated by standard deviation ). In order to achieve statistical stability, all the simulations have an ensemble size of 100. Quantum effect is taken into account by density-gradient method. Results and Discussion: Fig. 3 shows that with the increase of Tsi, ideal FinFETs’ Vt,lin decreases almost linearly while Vt,sat drops dramatically. The outcome of SCEs is unavoidable because the gate controllability of the front and back gates reduces when fin is widened. However, TG structure performs better than DG structure in the suppression of the SCEs due to the top gate’s control over channel. Fig. 4 plots ideal FinFETs’ DIBL value as a function of Tsi, showing TG devices’ advantage to suppress SCEs when fin is widened. Fig. 5 shows that with the increase of Tsi, ideal FinFETs’ Ion rises almost linearly and Ioff rises almost exponentially. It is noticed that TG devices’ benefits such as larger drive current and smaller leakage current do not appear until Tsi exceeds half the channel length (10nm). Fig. 6 shows that fin LER contributes to a remarkable increase of threshold voltage, and the thinner the fin is, the more Vt,lin shifts. This is because the quasi-continuous conduction band splits into a series of discrete sub-bands due to quantum confinement effect. The thinner the fin is, the more notable this effect becomes. Fig. 6 also shows with the same Tsi, Vt,lin’s shifts are less remarkable in TG devices than in DG devices. Thus, TG FinFETs with wider fin present a potential ability to reduce fin LER effects. However, widening the fin should be treated carefully, for it may exacerbate the SCEs as shown in Fig. 7. Fortunately, DIBL does not rise as aggressively as expected in TG devices, noting that in Fig. 7 rough FinFETs with TG structure have a lower DIBL than that of ideal FinFETs. Another drawback of widening fin is the exponentially increase of leakage current as shown in Fig. 8. However, the leakage current of rough FinFETs does not rise as aggressively as expected in ideal FinFETs because fin LER contributes to a significant increase of threshold voltage. Additionally, it can be seen in Fig. 8 that when fin is thin, TG devices even have a larger Ioff than DG devices, because at this region Ioff is dominated by gate leakage current rather than sub-threshold leakage current, and TG devices have a relatively larger area of gate. TG devices’ superiority in lowering leakage current does not appear until the fin is wide enough (eg. 20nm). Fig. 9 shows that with the increase of Tsi, the fluctuations of Vt,lin drop almost linearly. Also TG devices present better consistency of threshold voltage under the influence of fin LER. Fig. 10 shows that with the increase of Tsi, the fluctuations of DIBL drop dramatically. Although the absolute value of DIBL increases when the fin is widened, the variation is weakened. The similar phenomenon can be observed in Fig. 11, which shows that with the increase of Tsi, the fluctuations of leakage current drop dramatically. Moreover, in Fig. 10 and Fig. 11, TG devices present superiority to DG devices in the suppression of the SCEs such as the increase of DIBL and leakage current. In summary, widening the fin inevitably brings about SCEs. However, using TG devices instead of DG devices can achieve better resistance to SCEs because of the top gate’s control over the channel. What makes more sense is that widening the fin can significantly reduce the shifts and fluctuations of device performance caused by fin LER effects. From our simulation above, we suggest relaxing fin-thickness constraints from less than one third of the channel length to half or even equal to the channel length. With the help of TG structure, FinFETs with optimized fin-thickness can reduce the influence of fin LER meanwhile suppress SCEs under a tolerable degree. Conclusion: By 3-D statistical simulation, we investigate the effects brought by widening the fin of ideal FinFETs with smooth line edge and rough FinFETs with fin LER. The results show that the benefits of widening fin to reduce shifts and fluctuations caused by fin LER outweigh the detriment of possibly enhanced SCEs. So we propose to relax the fin-thickness constraints to achieve better resistance to fin LER effects. In the meantime, we propose to use triple-gate FinFETs to replace the conventional double-gate FinFETs to help suppress SCEs after fin is widened. Our simulation provides guidelines for designing FinFETs device to reduce intra-die fluctuations. Acknowledgement: This work is supported by NKBRP2006CB302705 and NSFC 60736030. Reference: [1] A. Asenov, et al, IEEE Trans. Electron Devices, Vol. 50, No. 9, pp. 1837-1852, Sep. 2003. [2] P. Oldiges, et al, in Proc. SISPAD, 2000, pp. 131–134. [3] B. Yu, et al, in IEDM Tech. Dig., 2002, pp. 251–254. [4] A. Dixit, et al, in IEDM Tech. Dig., 2006, pp. 709–712. [5] E. Baravelli, et al, IEEE Trans. Electron Devices, Vol. 54, No. 9, pp. 2466–2474, Sep. 2007. [6] G. Pei, et al, IEEE Trans. Electron Devices, Vol. 49, No. 8, pp. 1411-1419, Aug. 2002. [7] S. Yu, et al, in Silicon Nanoelectronics Workshop, 2008. [8] ISE-TCAD tools from Integrated System Engineering (ISE). Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008,