Jorge Grilo

A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver

A 12 mW switched-capacitor (SC) multi-bit ADC delta-sigma modulator for baseband demodulation integrated in a single-chip Bluetooth radio-modem transceiver achieves 77 dB of SINAD and 80 dB of dynamic range over a 500 kHz bandwidth with a 32 MHz sample-rate. The 1 mm/sup 2/ circuit is implemented in a 0.35 /spl mu/m BiCMOS SOI process and operates from a 2.7 V supply.

A direct-conversion single-chip radio-modem for bluetooth

A fully-integrated radio-modem using a direct-conversion receiver architecture achieves -83 dBm sensitivity at 0.1% BER, +40 dBm IIP2, and -5 dB and -40 dB adjacent and alternate channel blocking C/I, respectively. The radio consumes 39 mA in receive and 37 mA in transmit mode with a 2.7 V supply. The 19.5 mm/sup 2/ chip uses a 0.35 /spl mu/m 27 GHz f/sub T/ SOI BiCMOS process.

High-linearity calibration of low-resolution digital-to-analog converters

We describe a high-precision calibrating system where the code error voltages of a low-resolution binary-weighted capacitor-array DAC, measured against the precise code voltage references generated by a single-capacitor pulse-counting DAC, are digitized and corrected using a small subbinary-weighted capacitor-array. Computer simulation results are given to demonstrate the operation of the proposed system and the benefits that can be gained by employing gain- and offset-compensated stages.<<ETX>>

Predictive correlated double sampling switched-capacitor integrators

This paper explores predictive correlated double sampling (CDS) as a means of achieving good linearity and low power dissipation in switched-capacitor (SC) integrators. The technique reduces the effect of the open-loop nonlinearity characteristic of an amplifier, thereby allowing the utilization of single-stage low-gain structures.

The use of predictive correlated double sampling techniques in low-voltage delta-sigma modulators

This paper explores predictive correlated double sampling (CDS) as a means of achieving good linearity and low power dissipation in low-voltage moderate-performance switched-capacitor (SC) delta-sigma modulators. The technique reduces the effect of the open-loop nonlinearity characteristic of an amplifier, thereby allowing the utilization of single-stage low-gain structures.

A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration

This paper presents a digitally calibrated 12bit 12.5-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) intended for low-power wireless communication and medical instrumentation. The performance of the proposed prototype is enhanced by two techniques. A power saving strategy is proposed. Also, several foreground calibration methods for SAR ADCs are proposed to reduce the power dissipation and enhance the conversion accuracy. The design was fabricated in the GlobalFoundries 40 nm CMOS technology. Measurement results showed that after calibration a SFDR of 87.5 dB and a THD improvement of 24.3 dB were achieved.

The realization of delta-sigma A/D converters in low-voltage digital CMOS technology

This paper discusses the design of high-linearity analog CMOS circuits in basic digital CMOS technology, which allows only low supply voltages and has a single polysilicon layer. The key design issues are described, and illustrated with the design details of two delta-sigma ADCs. The first features a very low (1.8 V) supply voltage and a 94 dB dynamic range, while the second one contains only MOSFETs, no capacitors or resistors, and achieved 94 dB peak S/THD and SNR.

Session 22 — High frequency analog techniques

Summary form only given. This session presents analog techniques applied to high-frequency applications found in RF systems & data acquisition systems. The first paper presents a tunable low-pass filter from 34-314 MHz with a 22 dBm IIP3 while consuming only 4.6 mW. The 3rd-order filter is constructed from inverter-based gm-cells and non-linear MOSCAPs, leveraging several distortion cancellation techniques. Additionally the filter resistors and capacitors are used to self-compensate the negative feedback circuits resulting in lower power and a very small circuit area of 0.007 mm2. The second paper presents a tunable RF bandpass filter with Q-tuning implemented in a 0.13 μm SiGe BiCMOS process. The filter is tunable from 2.25-4.5 GHz with independent Q-tuning from 3-150. Linearity is improved by using a dual varactor for tuning such that the varactor 3rd order distortion cancels over the range where the MOS varactors are the most nonlinear. This results in an out-of-band IIP3 of 23.5 dBm. The third paper presents an injection locked PLL (ILPLL) at 2 GHz fabricated in a 65nm CMOS process consuming 3.74 mW form 0.9 V. Traditional ILPLLs use a tunable delay line to inject the reference pulse into the oscillator and require delay line calibration to ensure proper timing of the pulse to minimize the reference spur. In this work, an injection locked frequency divider (ILFD) is used to introduce a phase shift in the feedback path of the ILPLL. This has the effect of locking the delay in the ILPLL to a fixed delay line resulting in a simple, low power calibration that can be run in the background. The fourth and final paper in the session leverages a 0.25 μm GaN HEMT process to implement a high SNR track-and-hold. The T/H provides a 98 dB SNR at 200 MHz for greater than 16-bit performance. The primary challenge in using a GaN process for T/H applications is related to the gate leakage associated with the Schottky contact gate. In this work a gate bootstrapping technique is used as well as a two-stage T/H to minimize droop in hold mode.

Sub-session: Data converter techniques

Data converters play an increasingly important role in communication systems. In order to support the demand for higher bandwidths and efficiency, recent work has focused both on architecture and ingenious circuit improvements that take advantage of the speed offered by nanometer-scale technologies.