Yuta Yamato

A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation

X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effectiveness of previous X-filling methods suffers from lack of guidance in selecting targets and values for X-filling. This paper addresses this problem with a highly-guided X-filling method based on two novel concepts: (1) X-score for X-filling target selection and (2) probabilistic weighted capture transition count for Y-filling value selection. Experimental results show the superiority of the new X-filling method for capture power reduction.

Power-aware test generation with guaranteed launch safety for at-speed scan testing

At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by excessive launch switching activity (LSA) caused by test stimulus launching in the at-speed test cycle. However, previous low-power test generation techniques can only reduce LSA to some extent but cannot guarantee launch safety. This paper proposes a novel & practical power-aware test generation flow, featuring guaranteed launch safety. The basic idea is to enhance ATPG with a unique two-phase (rescue & mask) scheme by targeting at the real cause of the launch safety problem, i.e., the excessive LSA in the neighboring areas (namely impact areas) around long paths sensitized by a test vector. The rescue phase is to reduce excessive LSA in impact areas in a focused manner, and the mask phase is to exclude from use in fault detection the uncertain test response at the endpoint of any long sensitized path that still has excessive LSA in its impact area even after the rescue phase is executed. This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of donpsilat care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification

Test data modification based on test relaxation and X-filling is the preferable approach for reducing excessive IR-drop in at-speed scan testing to avoid test-induced yield loss. However, none of the existing test relaxation methods can control the distribution of identified donpsilat care bits (X-bits), thus adversely affecting the effectiveness of IR-drop reduction. In this paper, we propose a novel test relaxation method, called Distribution-Controlling X-Identification (DC-XID), which controls the distribution of X-bits identified from a set of fully-specified test vectors for the purpose of effectively reducing IR-drop. Experimental results on large industrial circuits demonstrate the effectiveness and practicality of the proposed method in reducing IR-drop, without any impact on fault coverage, test data volume, or test circuit size.

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency.

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing

Reducing excessive launch switching activity (LSA) is now mandatory in at-speed scan testing for avoiding test-induced yield loss, and test set modification is preferable for this purpose. However, previous low-LSA test set modification methods may be ineffective since they are not targeted at reducing launch switching activity in the areas around long sensitized paths, which are spatially and temporally critical for test-induced yield loss. This paper proposes a novel CAT (Critical-Area-Targeted) low-LSA test modification scheme, which uses long sensitized paths to guide launch-safety checking, test relaxation, and X-filling. As a result, launch switching activity is reduced in a pinpoint manner, which is more effective for avoiding test-induced yield loss. Experimental results on industrial circuits demonstrate the advantage of the CAT scheme for reducing launch switching activity in at-speed scan testing.

A novel scan segmentation design method for avoiding shift timing failure in scan testing

High power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme.

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment

Reducing IR-drop in the test cycle during at-speed scan testing has become mandatory for avoiding test-induced yield loss. An efficient approach for this purpose is post-ATPG test modification based on X-identification and X-filling since it causes no circuit/clock design change and no test vector count inflation. However, applying this approach to test compression has been considered challenging due to the limited availability of X-bits. This paper solves this serious problem by proposing a novel and practical CA (Compression-Aware) test modification scheme for reducing IR-drop in the widely-used broadcast-scan based test compression environment. This unique scheme features (1) CA circuit remodeling for minimizing the effort of applying test modification to broadcast-scan-based test compression, (2) CA X-identification for increasing X-bits for risky test vectors, and (3) CA X-filling for effectively using limited X-bits in reducing IR-drop. As a result, the CA test modification scheme can achieve significant IR-drop reduction even when a test cube only has a small number of X-bits. This advantage is clearly demonstrated by experimental results on three compression configurations created from an industrial circuit.

A Per-Test Fault Diagnosis Method Based on the X-Fault Model

This paper proposes a new per-test fault diagnosis method based on the X-fault model. The X-fault model can represent all possible faulty behaviors of a physical defect or defects in a gate and/or on its fanout branches by assigning different X symbols assigned to the fanout branches. A partial symbolic fault simulation method is proposed for the X-fault model. Then, a novel technique is proposed for extracting more diagnostic information by analyzing matching details between observed and simulated responses. Furthermore, a unique method is proposed to score the results of fault diagnosis. Experimental results on benchmark circuits demonstrate the superiority of the proposed method over conventional per-test fault diagnosis based on the stuck-at fault model.