Yutaka Hojo

SEM-contour shape analysis method for advanced semiconductor devices

The new measuring method that we developed executes a contour shape analysis that is based on the pattern edge information from a SEM image. This analysis helps to create a highly precise quantification of every circuit pattern shape by comparing the contour extracted from the SEM image using a CD measurement algorithm and the ideal circuit pattern. The developed method, in the next phase, can generate four shape indices by using the analysis mass measurement data. When the shape index measured using the developed method is compared the CD, the difference of the shape index and the CD is negligibly small for the quantification of the circuit pattern shape. In addition, when the 2D patterns on a FEM wafer are measured using the developed method, the tendency for shape deformations is precisely caught by the four shape indices. This new method and the evaluation results will be presented in detail in this paper.

Shot number analysis at 65-nm node mask writing using VSB writer

It depends for the writing time of variable shaped electron-beam (VSB) writing system on the number of writing shots. For shortening of writing time, it is most effective to reduce the number of shots. However, Resolution Enhancement Technologies (RET), such as OPC and PSM, make the VSB shot number increase explosively, in addition to reduction of LSI pattern size, and worsens the writing throughput. This is a serious problem for VSB mask writer, and the improvement of a writing throughput is required. In order to solve this problem, we inquired towards diversifying beam shape only from a rectangle. First, we investigated about the curtailment effect of the number of shots by trapezoid aperture adoption. Some latest VSB writer has adopted a triangle shaped aperture to compose the slanting figure in the LSI pattern efficiently. We investigated the efficiency of forming the slanting figure with trapezoid or parallelogram apertures compared with initial triangle aperture shot number. As the result of that, shown in Fig.1, we obtained the result that the shots number was reduced into 50% or more compared with initial triangle shots number. And, we examined a possibility of uniting and applying the character projection (CP) technique, which is adopted as EB direct writing (DW), to mask writing. Since pattern size is, for example, 4 times larger in the case of mask writing compared with the case of EBDW, the area that can extract a common CP pattern out from LSI patterns at mask writing is smaller than EBDW. Then, we extracted CP aperture pattern from cell library data for logic LSI. We obtained the result, shown in Fig.2, that the shot number that was used CP aperture was reduced into about 35% compared with initial VSB shots number. However, the arrangement number of aperture has restriction, and if the arrangement number decreases, the curtailment rate of the shots number will fall. These two techniques are fundamentally effective in curtailment of writing shots number. Furthermore, we will discuss with the possibility of applying these techniques to mask writing and with some problems to solve for the application of these techniques.

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process

Abstract. The model accuracy of optical proximity-effect correction (OPC) was investigated by two modeling methods for a 10-nm node process. The first method is to use contours of two-dimensional structures extracted from critical dimension-scanning electron microscope (CD-SEM) images combined with conventional CDs of one-dimensional structures. The accuracy of this hybrid OPC model was compared with that of a conventional OPC model, which was created with only CD data, in terms of root-mean-square (RMS) error for metal and contact layers of 10-nm node logic devices. Results showed improvement of model accuracy with the use of hybrid OPC modeling by 23% for contact layer and 18% for metal layer, respectively. The second method is to apply a correction technique for resist shrinkage caused by CD-SEM measurement to extracted contours for improving OPC model accuracy. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total RMS error was decreased by 12% by using the shrink correction technique. It can be concluded that the use of CD-SEM contours and the shrink correction of contours are effective to improve the accuracy of OPC model for the 10-nm node process.

SEM-contour shape analysis based on circuit structure for advanced systematic defect inspection

We have developed a practicable measurement technique that can help to achieve reliable inspections for systematic defects in advanced semiconductor devices. Systematic defects occurring in the design and mask processes are a dominant component of integrated circuit yield loss in nano-scaled technologies. Therefore, it is essential to ensure systematic defects are detected at an early stage of wafer fabrication. In the past, printed pattern shapes have been evaluated by human eyes or by taking manual critical dimension (CD) measurements. However, these operations are sometimes unstable and inaccurate. Last year, we proposed a new technique for taking measurements by using a SEM contour [1]. This technique enables a highly precise quantification of various complex 2D shaped patterns by comparing a contour extracted from a SEM image using a CD measurement algorithm and an ideal pattern. We improved this technique to enable the carrying out of inspections suitable for every pattern structure required for minimizing the process margin. This technique quantifies a pattern shape of a target-layer pattern using information on a multi-layered circuit structure. This enabled it to confirm the existence of a critical defect in a circuit connecting upper/lower-layers. This paper describes the improved technique and the evaluation results obtained in evaluating it in detail.

Focus measurement using SEM image analysis of circuit pattern

We have developed a new focus measurement method based on analyzing SEM images that can help to control a scanner. In advanced semiconductor fabrication, rigorous focus control of the scanner has been required because focus error causes a defect. Therefore, it is essential to ensure focus error are detected at wafer fabrication. In the past, the focus has been measured using test patterns made outside of the chip by optical metrology system. Thus, present focus metrology system can’t measure the focus of an arbitrary point in the chip. The new method enables a highly precise focus measurement of the arbitrary point of the chip based on a focus plane of a reference scanner. The method estimates the focus amount by analyzing side wall shapes of circuit patterns of SEM images. Side wall shapes are quantified using multisliced contours extracted from SEM-images high accuracy. By using this method, it is possible to measure the focus of the arbitrary circuit pattern area of the chip without a test pattern. We believe the method can contribute to control the scanner and to detect hot spots which appear by focus error. This new method and the evaluation results will be presented in detail in this paper.

Hybrid OPC modeling with SEM contour technique for 10nm node process

Hybrid OPC modeling is investigated using both CDs from 1D and simple 2D structures and contours extracted from complex 2D structures, which are obtained by a Critical Dimension-Scanning Electron Microscope (CD-SEM). Recent studies have addressed some of key issues needed for the implementation of contour extraction, including an edge detection algorithm consistent with conventional CD measurements, contour averaging and contour alignment. Firstly, pattern contours obtained from CD-SEM images were used to complement traditional site driven CD metrology for the calibration of OPC models for both metal and contact layers of 10 nm-node logic device, developed in Albany Nano-Tech. The accuracy of hybrid OPC model was compared with that of conventional OPC model, which was created with only CD data. Accuracy of the model, defined as total error root-mean-square (RMS), was improved by 23% with the use of hybrid OPC modeling for contact layer and 18% for metal layer, respectively. Pattern specific benefit of hybrid modeling was also examined. Resist shrink correction was applied to contours extracted from CD-SEM images in order to improve accuracy of the contours, and shrink corrected contours were used for OPC modeling. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total error RMS was decreased by 0.2nm (12%) with shrink correction technique. Variation of model accuracy among 8 modeling runs with different model calibration patterns was reduced by applying shrink correction. The shrink correction of contours can improve accuracy and stability of OPC model.