Yuuichi Aoki

A single-chip 16-bit 25-ns real-time video/image signal processor

A single-chip real-time video/image processor (VISP) has been developed that integrates functions based on a variable seven-stage pipeline arithmetic architecture in a 16-bit fixed-point data format. A three-input adder implemented in complementary CMOS reduced-swing logic, which is twice as fast as conventional CMOS logic, achieving a 25-ns instruction cycle, is shown. Single-VISP processing times are: edge detection (3*3 Laplacian), 14.8 ms; distance calculation, 1.7 ms; temporal filtering (1-tap IR), 5.0 ms; linear quantization, 3.3 ms; and 3/5*3/5 picture reduction (separate 5-tap FIR), 5.9 ms. An example is shown of a two-dimensional discrete cosine transformation which requires 26.3 ms to execute with one VISP when 256*256 pixel processing at a 25-ns instruction cycle is employed.<<ETX>>

A diplexer-matching dual-band power amplifier LTCC module for IEEE 802.11a/b/g wireless LANs

We have developed a compact dual-band (2.4/5 GHz) power-amplifier module with a concurrent two-stage InGaP/GaAs HBT for triple-mode (IEEE 802.11a/b/g) WLANs. The proposed diplexer-matching network is three-dimensionally implemented in an LTCC substrate (5/spl times/5 mm). The module exhibits an output power of 20 dBm at 2.4 GHz, and 18 dBm at 5.25 GHz with an error vector magnitude of 4-5% for a 54-Mbps OFDM signal. Our approach of using a concurrent dual-band PA reduces the size and cost by almost half compared with using a conventional parallel PA.

A 1.4-dB-NF variable-gain LNA with continuous control for 2-GHz-band mobile phones using InGaP emitter HBTs

We designed a continuously variable-gain low-noise-amplifier (VG-LNA) circuit with a noise figure (NF) of 1.4 dB. This VG-LNA has a diode-loaded emitter follower and a variable-current source. The diode-loaded emitter follower enables gain control without NF degradation at the maximum gain; the variable-current source improves the linearity and widens the range of gain control. It was fabricated by using InGaP-emitter heterojunction bipolar transistors (HBTs) and has an NF of 1.4 dB at maximum gain, 1.95 GHz, and a 3-V supply voltage. Its maximum gain is 15 dB, its input 3rd-order-intercept-point (IIP3) at the maximum gain is 3.4 dBm, and the gain-control range is 40 dB. The obtained of NP of 1.4 dB is the lowest so far reported for a continuously controlled VG-LNA.

Analysis and Design of a Dynamic Predistorter for WCDMA Handset Power Amplifiers

This paper presents a dynamic predistorter (PD), which linearizes the dynamic AM-AM and AM-PM of a wideband code division multiple access handset power amplifier (PA). The dynamic PD allows an adjacent channel leakage power ratio (ACPR) improvement of 15.7 dB, which is superior to conventional PDs that linearize static AM-AM and AM-PM. The dynamic PD was designed using an HBT generating nonlinearity, a short circuit at the baseband (les4 MHz), and a load circuit for the HBT at the RF fundamental band (ap1.95 GHz). Volterra-series analysis was performed to understand the mechanism of the dynamic PD. The analysis revealed that the short circuit at the baseband enabled the dynamic PD generating third-order intermodulation distortion (IMD3) with opposite phase to the fundamental tone (i.e., antiphase IMD3). The antiphase IMD3 allows dynamic gain compression, which linearizes the dynamic gain expansion of a PA with low quiescent current. The analysis also revealed that the IMD3 amplitude of the dynamic PD can be adjusted by load impedance at the RF fundamental band, which enables the gradient of dynamic AM-AM and AM-PM to be optimized to linearize the PA. The fabricated two-stage InGaP/GaAs HBT PA module with the dynamic PD exhibited an ACPR of -40 dBc and a power-added efficiency of 50% at an average output power of 26.8 dBm with a quiescent current of 20 mA

A 20-mA quiescent current two-stage W-CDMA power amplifier using anti-phase intermodulation distortion

This paper explains how the adjacent-channel-leakage-power ratio (ACLR) of power amplifiers (PAs) can be reduced by using gain-expansion amplifiers in tandem and generating anti-phase intermodulation distortion (IMD) in the driver stage to cancel the IMD in the output stage. The power-added-efficiency (PAE) can thus be increased by using near-class-B-biased driver- and output-stage amplifiers, which inherently have gain-expansion characteristics and high PAE at low output power as well as at maximum output power. At a supply of 3.5 V and an output power of 27.1 dBm, the fabricated PA with a quiescent current of only 19.8 mA exhibited a PAE of 44%, a gain of 25.2 dB, and an ACLR of less than -38.0 dBc. This is state-of-the-art performance for a two-stage W-CDMA PA with an extremely low quiescent current.

A 0.08-cc fully integrated LTCC transceiver front-end module for 5-GHz wireless LAN systems

An extremely compact transceiver (TRx) front-end module (FEM) has been developed for 5-GHz wireless LAN systems. A highly-integrated flip-chip TRx IC and the embedding of passive devices in a low-temperature co-fired ceramic (LTCC) with high /spl epsi//sub r/(=17) are the keys to reducing the module size to 8 /spl times/ 10 /spl times/ 1 mm (0.08 cc). To the best of our knowledge, this is the most compact existing FEM that demonstrates full transceiver operation and complies with the IEEE 802.11a standard.

A 23/3-dB dual-gain low-noise amplifier for 5-GHz-band wireless applications

We have developed a wide-dynamic-range low-noise amplifier (LNA) based on InGaP/GaAs hetero bipolar transistors (HBTs) for 5-GHz-band wireless applications. With no external matching components, this dual-gain LNA (with a 20-dB gain attenuation function) has a very high performance; namely, a noise figure (NF) of 2.3 dB, a gain of 23 dB, an output 1-dB compression point(P/sub 1dB/) of 9.8 dBm, and a DC power consumption (P/sub dc/) of 28 mW at 3.0 V. Its figure of merit, defined as (gain/NF)/spl middot/(P/sub 1dB//Pd/sub dc/), is 3.3, which is the highest value in the C-band to date.

50% PAE 20-mA quiescent current W-CDMA power amplifier with on-chip dynamic-gain linearizer

This paper explains a power-effective linearization technique for power amplifiers (PAs) having gain-expansion characteristics. A new on-chip dynamic-gain-deviation cancellation circuit improves the adjacent-channel-leakage-power ratio (ACLR) for a W-CDMA signal by 11 dB. At a supply of 3.5 V and an output power of 26.9 dBm, a fabricated PA with a quiescent current (Iq) of 19 mA exhibited a power-added efficiency of 50%, a gain of 26 dB, and an ACLR of -40 dBc. Furthermore, when we applied this technique to a PA with Iq of only 10-mA, this PA also satisfied the W-CDMA criteria.

A low-power and variable-gain transceiver front-end chip for 5-GHz-band WLAN applications

A low-power 5-GHz-band transceiver front-end chip is described that uses highly reliable, high-performance InGaP/GaAs HBTs and complies with IEEE802.11a standards. Integrated into the chip (2.4/spl times/2.4 mm/sup 2/) are a 20/0-dB dual-gain low-noise amplifier and a wide IF-range down-conversion mixer in the receiver path, a 20-dB variable-gain driver amplifier and a low and stable local oscillator (LO) leakage up-conversion mixer in the transmitter path, and a high-isolation LO buffer. Very low power consumption (120 mW) is attained with a single 3-V supply voltage in receiver mode together with high transceiver performance. The key features and new circuit approaches in each function block are described in details. Measurement showed that a 5-GHz OFDM-modulated Tx signal meets IEEE802.11a standards.

A Wireless Dual-Link System for Sensor Network Applications

A reduced-power-consumption wireless ad-hoc multi-hop network system, the dual-link system,is been developed, using the following two technologies: Dual-link communication, which handles two different frequency bands, achieves low-power data transmission through independent optimum settings of both operation periods and communication distances for each band. The selection of frequency bands and operation settings depends on both the data sizes and communication intervals defined for individual applications. This dual-link communication is applicable to various kinds of intermittent communications. A vine-tree network topology that offers low addressing-bit counts and results in low packet-error rates even in low transmission-power communications. Since the topology does not require a routing table for individual nodes, hardware complexity can be kept to a minimum.