Hikaru Hida

An investigation of i-AlGaAs/n-GaAs doped-channel MIS-like FET's (DMT's)—Properties and performance potentialities

Doped-channel MIS-like FETs (DMTs) based upon an i-AlGaAs/n-GaAs structure have been investigated in detail for the purpose of clarifying their properties and performance potentialities. The DMT is unique in having two operation modes, a depletion-layer modulation mode and an electron accumulation mode, both of which are experimentally demonstrated through capacitance-voltage characteristics. Analytical and experimental results shows that the maximum drain current IDSmaxis more than 2.5 times that for a conventional n-AlGaAs/GaAs 2DEGFET. gmmaxand IDsmaxvalues obtained for 0.5- µm gate DMTs are very high, 310 mS/mm (410 mS/mm) and 650 mA/mm (800 mA,/mm) at 300 K (77 K), respectively, fmaxis 48 GHz. fTis as large as 45 GHz, which is the best data ever reported in 0.5-µm gate FETs. Moreover, the estimated electron saturation velocity is outstandingly large, 1.5 × 107cm/s (2 × 107cm/s) at 300 K (77 K), even for a thin GaAs channel layer with a 3 × 1018cm-3doping level, while Hall electron mobility is not reasonably so high, being typically 1850 cm2/V . s (1650 cm2/V . S). Preliminary power performances are also studied at 28.5 GHz. An 18-dBm (225-mW/mm) saturation output power, 6.4-dB linear gain, and 15-percent power added efficiency are achieved. A further performance improvement may be easily accomplished by gate length reduction, structure optimization, and so on. Consequently, it has been proved that DMTs have great feasibility for high-speed and high-frequency high-power device applications.

A high-current drivability i-AlGaAs/n-GaAs doped-channel MIS-Like FET (DMT)

A high-current drivability doped-channel MIS-like FET (DMT) has been proposed. The DMT takes advantage of high saturation current with large transconductance and high breakdown voltage, in regard to its operating principle. The fabricated 0.5-µm gate DMT showed 310-mS/mm (410-mS/mm) transconductance and 650-mA/mm (800-mA/mm) maximum saturation current at room temperature (at 77 K). Output current values are about three or four times those for conventional two-dimensional electron gas (2DEG) FETs. Estimated average electron velocity is rather high, 1.5 × 107cm/s (2 × 107cm/s) at room temperature (77 K). In addition,f_{\max}is as high as 41 GHz. fTis 45 GHz, which is the best data ever reported in 0.5-µm gate FETs.

Low-power widely tunable Gm-C filter with an adaptive DC-blocking, triode-biased MOSFET transconductor

We propose a new transconductor to achieve a wide continuous-tuning-range filter applicable to IEEE802.11a/b/g W-LANs, W-CDMA, and Bluetooth, without sacrificing power consumption. The wide tuning range is achieved by employing triode-biased input MOSFETs, whose transconductance is widely tuned with drain bias. The transconductor also employs an adaptive DC-blocking circuit that suppresses any idle current in the high transconductance mode, resulting in minimizing the power consumption of the transconductor. A 4th-order Butterworth low-pass filter, using this new transconductor, exhibits a cutoff frequency tuning range of 0.5-12 MHz with power consumption of 1.1-4.7 mW. The tuning range is 5 times wider than other works with low power consumption.

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

A low-power dual-band triple-mode WLAN CMOS transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively

A new low-noise AlGaAs/GaAs 2DEG FET with a surface undoped layer

A high-performance N-AlGaAs/GaAs selectively doped two-dimensional electron gas (2DEG) FET with a surface undoped layer has been designed and demonstrated. Simple analysis based on the short-channel approximation revealed that an increase in a total layer thickness between a gate electrode and 2DEG at a hetero-interface results in a higher cutoff frequency and a lower noise figure than conventional 2DEG FETs. This is because the gate capacitance can be markedly reduced without a significant decrease in the transconductance owing to a parasitic source resistance. The surface undoped layer intentionally employed in this work can permit the total layer thickness to increase, i.e., the gate capacitance to reduce, without changes in the 2DEG density and in the source resistance. This structure also gives high gate breakdown voltage because of a small neutral region in n- (AlGa)As and a low surface electron field, which possibly yields excellent performance 2DEG FETs for practical use. Fabricated (AlGa)As/ GaAs 2DEG FETs exhibited noticeable room-temperature performances of 0.95-dB noise figure with 10.3-dB associated gain at 12- and 45-GHz cutoff frequency. These are the best data ever reported for 0.5-µm gate length FETs.

A diplexer-matching dual-band power amplifier LTCC module for IEEE 802.11a/b/g wireless LANs

We have developed a compact dual-band (2.4/5 GHz) power-amplifier module with a concurrent two-stage InGaP/GaAs HBT for triple-mode (IEEE 802.11a/b/g) WLANs. The proposed diplexer-matching network is three-dimensionally implemented in an LTCC substrate (5/spl times/5 mm). The module exhibits an output power of 20 dBm at 2.4 GHz, and 18 dBm at 5.25 GHz with an error vector magnitude of 4-5% for a 54-Mbps OFDM signal. Our approach of using a concurrent dual-band PA reduces the size and cost by almost half compared with using a conventional parallel PA.

A high-power-handling GSM switch IC with new adaptive-control-voltage-generator circuit scheme

We propose a high-power-handling switch circuit using a new adaptive-control-voltage-generator circuit (AVG). This AVG enables the internal control node voltages to be automatically increased in high-input-power conditions. This switch circuit results in high-power-handling, low-insertion-loss, small chip size and low voltage control. The developed IC demonstrated a handling power of 36.5 dBm and an insertion loss of 0.31 dB with 40% chip size reduction.

A +2.4/0 V controlled high power GaAs SPDT antenna switch IC for GSM application

We have developed a high-power-handling and low-voltage-controlled GaAs single-pole dual-throw (SPDT) antenna switch for GSM application. The switch circuit configuration has a capacitor at the antenna terminal and two resistors between the transmitter (Tx) and receiver (Rx) terminals and the control terminals. This circuit enables the DC voltages of the Tx terminal and the Rx terminal to be separated from each other, resulting in a high-power-handling operation at a lower control voltage than that for the conventional switch. The developed SPDT switch demonstrated a handling power of 37.5 dBm and an insertion loss of 0.37 dB with a control voltage of +2.4/0 V.

A novel 2DEGFET model based on the parabolic velocity-field curve approximation

A new model for selectively doped heterostructure two-dimensional electron gas (2DEG) FETs has been proposed. In order to take into account the strong field dependence of the 2DEG mobility, a parabolic approximation is employed for a velocity-field curve below a velocity saturation field. The nonlinear field dependence of parasitic resistances has also been considered, which is of great importance for a more accurate description of actual FET characteristics. The proposed FET model is very useful for a digital IC design, since it has fewer fitting parameters and gives a smooth fit to measured data. Good agreement between the calculated drain current-voltage characteristics and the experimental characteristics, both for short-gate FETs and for long-gate FETs, demonstrates the validity of the present model. In addition, it has been recently found from the analysis that a transconductance compression is possible caused by a current limitation, due to hot electrons in the source-to-gate region, even though the n-(AlGa)As layer is totally depleted.