Nobuhide Yoshida

250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

A 3.3-V 512-k/spl times/18-b/spl times/2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm/sup 2/, which is the same die size as the conventional DRAM, has been achieved with 0.50-/spl mu/m CMOS process technology. >

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

A low-power dual-band triple-mode WLAN CMOS transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively

A widely tunable CMOS Gm-C filter with a negative source degeneration resistor transconductor

We propose a new negative source degeneration resistor (NSDR) transconductor to achieve a wide continuous-tuning range gm-C filter applicable for IEEE802.11a/b/g wireless-LANs and W-CDMA. The NSDR-transconductor using a source degeneration resistor and positive feedback differential amplifier that acts as a negative resistor. This configuration enables the equivalent source degeneration resistance to be drastically increased without degrading linearity, thus resulting in a wide gm tuning. A 6th -order elliptic low-pass filter using this NSDR-transconductor exhibits a cutoff frequency (f/sub c/) tuning range of 1.5-12MHz, which is two times wider than that of conventional filters. Additionally, we introduce a new figure of merit (FoM) evaluating the basic filter performance. This filter shows 0.35 fj (FoM) in the IEEE802.11a mode, which is, to our best knowledge, the best value in the CMOS channel-select filters.

A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback

40-Gb/s clock and data recovery (CDR) circuit with an integrated high-precision eye-opening monitor (EOM) circuit and an adaptive control scheme for optimizing the data decision point are presented. An adaptive decision-point control (ADPC) scheme using the EOM feedback overcomes the time-varying waveform distortion due to transmission impairment, which causes severe degradation of bit-error-rate (BER) performance in high-speed (>40 Gb/s) data link systems. A 2.5 times 2.0-mm prototype chip is implemented in 0.18 -mum SiGe BiCMOS technology. The power consumption is 1.6 W with a +3.3-V supply voltage. Stable CDR operation with low-jitter performance (189 fs-rms) and the ADPC scheme using EOM feedback are demonstrated at 40 Gb/s. For a 30% duty-distorted 53 -mV signal, the proposed ADPC scheme drastically reduces the BER to le-12 compared to that (2e-7) without adaptive control. The experimental results demonstrate that the proposed CDR circuit greatly improves BER performance and provides robust CDR operation in high-speed data link systems.

A 100 Gb/s transceiver with GND-VDD common-mode receiver and flexible multi-channel aligner

A 5 Gb/s 20-channel transceiver uses 0.13 /spl mu/m 1.5 V CMOS technology. The sampling amplifier recovers /spl plusmn/100 mV 90 ps data over 0-1.5 V common-mode range. A flexible multi-channel aligner and full-digital CDR (clock/data recovery) architecture are used.

Real-time current-waveform sensor with plugless energy harvesting from AC power lines for home/building energy-management systems

Home/building energy-management systems (EMSs) driven by information technology are expected to be key to the achievement of an upgraded energy infrastructure, such as Smart Grid. While EMS may offer monitoring, reporting, and control of energy usage, these functions simply track intermittently the energy consumption and operational states of certain appliances and equipments. Further, since their sensing devices are not small, they cannot be attached to every appliance or piece of equipment. Some EMSs gather information, rather, at the power-distribution-board level or the multi-output-tap level. We report here a TX-integrated battery-free real-time current-waveform sensor. It is small enough to be attached to any piece of equipment for continuous power-consumption monitoring. Its key features are : 1) plugless energy harvesting (EH) from AC power lines, 2) real-time sensing and transmitting that use a half-cycle time-to-digital convertor (TDC) to detect detailed information on current-waveforms with the precise time-resolution, and 3) asymmetrical power consumption, which helps to achieve high-power RF transmission with a limited EH power supply. Our sensor provides the 1mW power supply from an EH unit, as well as the −5.5dBm RF output power at the 50kS/s sampling with a 1mW EH power supply. We also demonstrate transmission of sensed current-waveform information of several appliances such as a hair dryer, a TV, a notebook PC.

A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback

In high-speed data link systems of over 40Gb/s, the data decision point in the CDR circuit is not often the optimum position of the eye diagram. The CDR circuit is fabricated using a 0.18 mum SiGe BiCMOS process. The ft and fmax are 200 GHz and 180 GHz, respectively. To overcome a severe degradation of BER performance due to this misalignment, a 40 Gb/s CDR circuit integrated with an adaptive decision-point control scheme by using an eye-opening monitor feedback is developed. The key approaches are 40 Gb/s high-precision eye-opening monitor (EOM) circuit to detect an optimum decision point, an adaptive decision-point control (ADPC) scheme by using the EOM feedback, a decision- point adjustable self-aligned phase detector to achieve the ADPC operation. The combination of these approaches improves both the BER performance and the stability of CDR operation.

A Wireless Dual-Link System for Sensor Network Applications

A reduced-power-consumption wireless ad-hoc multi-hop network system, the dual-link system,is been developed, using the following two technologies: Dual-link communication, which handles two different frequency bands, achieves low-power data transmission through independent optimum settings of both operation periods and communication distances for each band. The selection of frequency bands and operation settings depends on both the data sizes and communication intervals defined for individual applications. This dual-link communication is applicable to various kinds of intermittent communications. A vine-tree network topology that offers low addressing-bit counts and results in low packet-error rates even in low transmission-power communications. Since the topology does not require a routing table for individual nodes, hardware complexity can be kept to a minimum.

A 35-to-46-Gb/s Ultra-Low Jitter Clock and Data Recovery Circuit for Optical Fiber Transmission Systems

We demonstrated an ultra-low jitter clock and data recovery (CDR) circuit that covers an ultra wide frequency range from 35 Gb/s to 46 Gb/s. Our CDR has a newly developed dual input LC-VCO with a fine/coarse tuning scheme and a dual-loop architecture, which consists of a phase tracking loop and a frequency tracking loop. The CDR chip, which was made using an InP-HBT process, shows an extremely clear eye opening with an ultra-low jitter (< 9 mUI-rms) and an error-free operation (<1times10-12) throughout a wide range of 35 to 46 Gb/s at a 231-1 PRBS signal. The RMS and peak-to-peak jitter of the recovered clock were 226 fs and 1.56 ps, respectively. We suppressed output jitter to half of that found in previous work. In addition, a stable bit error rate (BER) that is insensitive to PRBS word length was demonstrated during an optical transmission test. These results show that our full-rate CDR is a very promising chip for 40-Gb/s-class optical transmission systems with the multi data rates.