Yuuji Kobayashi

Rigorous simulation of exposure over nonplanar wafers

Standard simulations of optical projection systems for lithography with scalar or vector methods of Fourier optics make the assumption that the wafer stack consists of homogeneous layers. We introduce a general scheme for the rigorous electromagnetic field (EMF) simulation of lithographic exposures over non-planar wafers. Rigorous EMF simulations are performed with the finite-difference time-domain (FDTD) method. The described method is used to simulate several typical scenarios for lithographic exposures over non-planar wafers. This includes the exposure of resist lines over a poly-Si line on the wafer with orthogonal orientation, the simulation of “classical” notch problems, and the simulation of lithographic exposures over wafers with defects.

A study of mask specification in spacer patterning technology

A spacer patterning technology (SP) has the possibility of extending optical lithography to below 40nm half-pitch devices. Since the spacer patterning process necessitates somewhat more complicated wafer process flow, the CD variation on wafers involves more process error sources compared with conventional exposure patterning process. This implies that, for the spacer patterning process innovation in determining specifications for each unit process is requried. In particular, it is important to determine mask-related specifications in order to select high-end mask fabrication strategies for mask writing tools, mask process development, materials, inspection tools, and so on. The purpose of this paper is to discuss how to consider mask specification in spacer patterning process for 40nm half-pitch and beyond.

Defectivity reduction studies for ArF immersion lithography

Immersion lithography is widely expected to meet the manufacturing requirements of future device nodes. A critical development in immersion lithography has been the construction of a defect-free process. Two years ago, the authors evaluated the impact of water droplets made experimentally on exposed resist films and /or topcoat. (1) The results showed that the marks of drying water droplet called watermarks became pattern defects with T-top profile. In the case that water droplets were removed by drying them, formation of the defects was prevented. Post-exposure rinse process to remove water droplets also prevented formation of the defects. In the present work, the authors evaluated the effect of pre- and post-exposure rinse processes on hp 55nm line and space pattern with Spin Rinse Process Station (SRS) and Post Immersion Rinse Process Station (PIR) modules on an inline lithography cluster with the Tokyo Electron Ltd. CLEAN TRACKTM LITHIUS TM i+ and ASML TWINSCAN XT:1700Fi , 193nm immersion scanner. It was found that total defectivity is decreased by pre- and post-exposure rinse. In particular, bridge defects and large bridge defects were decreased by pre- and post-exposure rinse. Pre- and post-exposure rinse processes are very effective to reduce the bridge and large bridge defects of immersion lithography.

Resist footing variation and compensation over nonplanar wafer

This paper reports a problem regarding DUV lithography on topographical substrate and solution for obtaining desired CD control and resist pattern shape. In our experiment, large footing for 250 nm resist pattern was observed when the resist pattern was transferred over polysilicon step pattern of 175nm in height. This pattern error is not negligible regarding device performance. The exposure tool used was a KrF scanner of NA0.6. Resist was 500 nm thick with no ARC. Computer simulation was used to demonstrate the amount of footing. A non-rigorous diffraction model did not recreate the footing appearance at the poly-Si step. However, a rigorous diffraction model of incident light in a cone recreated the footing amount at the poly-Si step faithfully. In this simulation, optical distribution in the resist over the nonplaner wafer was solved by the FDTD method. Optical intensity at sidewall of the step differs between the two models. Experimental results as well as simulation results showed that the amount of the footing depended on a coherency factor of illumination. Larger coherency resulted in larger footing. In the case of a large coherency the illumination rays come from various directions to the wafer, and a large shadow area is likely to appear behind the steep step. As a consequence, optical behavior in the vicinity at the steep step has a strong impact on the resist footing.

Novel lithography design and verification methodology with patterning failure

We make a new model for pattern failure, which is the pattern collapse and bridging of resist patterns of 43-nm 1:1 lines and spaces (L/S) exposed as a focus-exposure matrix, to explain and predict the process window of the pattern failure. It is found that the conventional Imax-Imin model cannot be fitted to the experimental pass/fail data. Instead of Imax and Imin, we select the critical dimension (CD) and normalized image log slope (NILS) as the model input. The new CD-NILS model corresponds well to the experimental pass/fail data. Good correspondence is assumed to be due to the properly selected model input. Pattern collapse, which occurs during the drying of the water at the rinse of the resist patterns, is expected to be accelerated by the smaller line CD and the larger line width roughness (LWR) due to smaller NILS. Pattern bridging, which occurs during resist development, is expected to be accelerated by the larger line CD and the larger LWR. The CD-NILS model predicts the process window precisely when a new process condition (a new illumination in this case) is adopted. It suggests that the CD-NILS model is a powerful methodology for predicting the process window to optimize the process condition and optimize the lithography design.

Mask specification guidelines in spacer patterning technology

We have studied both the mask CD specification and the mask defect specification for spacer patterning technology (SPT). SPT has the possibility of extending optical lithography to below 40nm half-pitch devices. Since SPT necessitates somewhat more complicated wafer process flow, the CD error and mask defect printability on wafers involve more process factors compared with conventional single-exposure process (SEP). This feature of SPT implies that it is very important to determine mask-related specifications for SPT in order to select high-end mask fabrication strategies; those are for mask writing tools, mask process development, materials, inspection tools, and so on. Our experimental studies reveal that both mask CD specification and mask defect specification are somehow relaxed from those in ITRS2007. This is most likely because SPT reduces mask CD error enhanced factor (MEF) and the reduction of line-width roughness (LWR).