Yves Morand

Bonded planar double-metal-gate NMOS transistors down to 10 nm

Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High-

In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.

\kappa

For the first time, we report electrical and physical characterization of metal-oxide-semiconductor (MOS) capacitors fabricated on 2.5/spl mu/m epitaxial germanium layers grown on (100) silicon. These capacitors were made using HfO/sub 2/ as the dielectric and TiN as the metal gate electrode. We have studied the influence of the Ge surface preparation on the MOS electrical characteristics. It is demonstrated that a surface anneal step in a NH/sub 3/ ambient before the HfO/sub 2/ deposition results in significant improvements in both the equivalent oxide thickness (EOT) and the gate leakage current. We show that it is possible to achieve Ge/GeON/HfO/sub 2//TiN gate stacks with an EOT of 0.7 nm and a leakage current of 0.84 A/cm/sup 2/ at -2 V gate bias. The better transport properties of Ge and these performances show the interest of Ge and GeOI for the ITRS advanced nodes.

Dielectrics, and Metallic Source/Drain

We present for the first time Gate-Last (GL) planar Fully Depleted (FD) SOI MOSFETs featuring both ultra thin silicon body (3-5 nm) and BOX (25 nm). Transistors with metal-last on high-k first (TiN/HfSiON) have been successfully fabricated down to 15nm gate length. We have thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. We report excellent ION, p=1020μA/μm at IOFF, p=100nA/μm at VDD=0.9V supply voltage for <;110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. This is explained by the high efficiency of the strain transfer into the ultra-thin channel, as evidenced by physical strain measurements (dark field holography).

Germanium/HfO/sub 2//TiN gate stacks for advanced nodes: influence of surface preparation on MOS capacitor characteristics

In this paper, we present a CMOS NiSi totally silicided (TOSI)-gate on SiON module, based on a single step silicidation of the junctions and the total gate, and demonstrate its industrial feasibility on SRAM demonstrators. The single step silicidation is achieved by the use of an ultra-low initial Si gate electrode and selective S/D epitaxy, which allows us to avoid any additional CMP step. We show excellent transistor morphology, good device results and first functional NiSi TOSI-gate SRAMs in a state-of-the-art industrial cell size indicating the potential of our TOSI integration module for LP applications

Gate-last integration on planar FDSOI MOSFET: Impact of mechanical boosters and channel orientations

We propose an original architecture adapted to the 10nm transistor node (pitch 64nm) for FDSOI technology. This structure features self-aligned contacts and a gate capping dielectric layer preventing any short in case of lithographic misalignment of contacts. 2D simulations are carried out to quantify parasitic capacitances. Technological solutions are then proposed to optimize this key parameter. Consequences are evaluated at the device and circuit scale. It is shown that the use of low-k materials, such as airgap spacers, is a solid option to meet the 10nm node specifications.