Zhang Wentong

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer (TSL) with linear variable doping (LVD) and further research on the TSL LVD with a multiple step field plate (MSFP), a breakdown voltage (BV) model is proposed and experimentally verified in this paper. With the two-dimensional Poisson equation of the silicon on insulator (SOI) device, the lateral electric field in drift region of the thin silicon layer is assumed to be constant. For the SOI device with LVD in the thin silicon layer, the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field (ENDIF), from which the reduced surface field (RESURF) condition is deduced. The drain in the centre of the device has a good self-isolation effect, but the problem of the high voltage interconnection (HVI) line will become serious. The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device. Based on this model, the TSL LVD SOI n-channel lateral double-diffused MOSFET (nLDMOS) with MSFP is realized. The experimental breakdown voltage (BV) and specific on-resistance (Ron,sp) of the TSL LVD SOI device are 694 V and 21.3 Ω-mm2 with a drift region length of 60 μm, buried oxide layer of 3 μm, and silicon layer of 0.15 μm, respectively.

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance (Ron,sp) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage Vd is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field EI and the breakdown voltage (BV) of ABE SOI are 545 V/μm and −587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low Ron,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results.

Theory and optimization of the power superjunction device

Based on the optimization idea of the electric field from the surface to the bulk, this paper summarizes the basic theory and the two types of analytical optimization methods of the super junction (SJ) device. The essential difference between the SJ and the conventional power MOS structure is: the former is the junction-type voltage sustaining layer with the periodic N/P dopings and the later is the resistance-type voltage sustaining layer with the single conductive type. The positive and negative charges satisfying the charge balance are introduced into the SJ voltage sustaining layer, which causes the two-dimensional electric field to realize the optimization from the surface to the bulk. The paper gives the concepts of the charge and potential electric fields, analyzes the non-full depletion and full depletion modes, introduces the mechanism of the transient process and forward biased safe operating area, discusses the equivalent substrate model and the optimized substrate conditions. Finally, the minimum specific on-resistance R on,min optimization methodology is proposed to give the R on,min for a given breakdown voltage V B. R on of the SJ is decreased significantly compared to that of the conventional power MOS with the same V B. The R on -V B relationship changes from the R on∝ V B2.5 to V B1.32 even V B1.03, leading to the SJ as the “milestone in high voltage power MOS device”

A high voltage SOI pLDMOS with a partial interface equipotential floating buried layer

A novel silicon-on-insulator (SOI) high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer (FBL) and its analytical model is analyzed in this paper. The surface heavily doped p-top layers, interface floating buried N+/P+ layers, and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance. On the condition of ESIMOX (epoxy separated by implanted oxygen), it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from −232 V of the conventional SOI to −425 V and the specific resistance Ron, sp is reduced from 0.88 to 0.2424 Ω·cm2.

A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance

A new SOI self-balance (SB) super-junction (SJ) pLDMOS with a self-adaptive charge (SAC) layer and its physical model are presented. The SB is an effective way to realize charges balance (CB). The substrate-assisted depletion (SAD) effect of the lateral SJ is eliminated by the self-adaptive inversion electrons provided by the SAC. At the same time, high concentration dynamic self-adaptive electrons effectively enhance the electric field (EI) of the dielectric buried layer and increase breakdown voltage (BV). EI = 600 V/?m and BV = ?237 V are obtained by 3D simulation on a 0.375-?m-thick dielectric layer and a 2.5-?m-thick top silicon layer. The optimized structure realizes the specific on resistance (Ron,sp) of 0.01319 ??cm2, FOM (FOM = BV2/Ron,sp) of 4.26 MW/cm2 under a 11 ?m length (Ld) drift region.