Zheng-lin Liu

The research of DPA attacks against AES implementations

This article examines vulnerabilities to power analysis attacks between software and hardware implementations of cryptographic algorithms. Representative platforms including an Atmel 89S8252 8-bit processor and a 0.25 μm 1.8 v standard cell circuit are proposed to implement the advance encryption standard (AES). A simulation-based experimental environment is built to acquire power data, and single-bit differential power analysis (DPA), and multi-bit DPA and correlation power analysis (CPA) attacks are conducted on two implementations respectively. The experimental results show that the hardware implementation has less data-dependent power leakages to resist power attacks. Furthermore, an improved DPA approach is proposed. It adopts hamming distance of intermediate results as power model and arranges plaintext inputs to differentiate power traces to the maximal probability. Compared with the original power attacks, our improved DPA performs a successful attack on AES hardware implementations with acceptable power measurements and fewer computations.

Low-power clock-less hardware implementation of the rijndael S-box for wireless sensor networks

Abstract The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks (WSN). The design challenges for an efficient WSN mainly lie in two issues: power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte (S-box) transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, 1) The composite field arithmetic in GF((24))2 was used to implement the compact datapath circuit; 2) A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit (ASIC) on 0.25 μm complementary mental oxide semiconductor (CMOS) process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high-performance cryptographic intellectual property (IP) core for the wireless sensor node chips.

Chaotic Encrypted Polar Coding Scheme for General Wiretap Channel

A wiretap channel is an important model for wireless communication. By applying an extended multiblock polar coding scheme, recent literature has achieved the secrecy capacity of a general wiretap channel (not necessary degraded or symmetric). However, this secure polar coding scheme of physical layer also limits the transmission rate of the main channel, which may fail to meet the demand of high transmission rate and strong transmission security for practical wireless transmission. In order to obtain a higher secrecy transmission rate than the physical layer coding scheme over a general wiretap channel, a cross-layer encryption and coding scheme is proposed in this paper. In the proposed scheme, an onetime-pad encryption and a secure key transmission is constructed by combining a chaos stream cipher with the extended multiblock polar coding scheme. As proved, the proposed scheme has achieved a high secrecy transmission rate than the former physical layer coding scheme under the constraints of reliability and strong security for a general wiretap channel.

Hardware implementation of negative selection algorithm for malware detection

It has been an important issue needing solved in the information security field to detect malware[4][5]. Negative selection algorithm as one of the core algorithm of artificial immune system, can be applied to detect malware. Negative selection algorithm based on binary coding is one of the most basic and important detecting model. But the application of negative selection algorithm mainly exist in the software and net work systems, there is not a ready-made approach to apply negative selection algorithm to detect malicious attacks for embedded system at present. This paper focuses in proposing an approach to add a hardware immune mechanism to the embedded processor to defense malicious attacks and improving the traditional negative selection algorithm so that we can actually apply the algorithm in malware detection for embedded system in further work.

A 2.45-GHz W-level output power CMOS power amplifier with adaptive bias and integrated diode linearizer

A high-linearity CMOS power amplifier (PA) operating at 2.45GHz for WLAN applications with adaptive bias and an integrated diode linearizer is presented. The PA adopts adaptive bias scheme to adjust the gate bias voltage of power transistors by tracking the output power of the first diver amplifier for efficiency enhancement. Diode-connected MOS transistor is used to compensate the nonlinearity of input capacitance ( C gs ) of power transistors for linearity improvement. The simulation results demonstrate a gain of 33.2dB, a maximum output power of 30.7dBm with 29% of peak power added efficiency (PAE) and -30dBc third-order intermodulation (IMD3) product at 26.4dBm output power, reaching to excellent tradeoffs between efficiency and linearity.

On-chip transformer using multipath technique with arithmetic-progression step sub-path width

A novel on-chip transformer architecture using multipath technique is presented. The newly proposed arithmetic-progression step sub-path width method is used to lower the current-crowding effect induced by the difference between the length of inner sub-path and that of outer sub-path. Full-wave electromagnetic simulated and measured results confirm the better performance of the proposed transformers than the conventional ones. These transformers will be useful in designing high-performance CMOS RF integrated circuits for wireless applications.