Zhimin Tan

Low Capacitance Through-Silicon-Vias With Uniform Benzocyclobutene Insulation Layers

Low capacitance is critical to the electric performance of through-silicon-vias (TSVs). This paper reports the development of a low capacitance TSVs by replacing silicon dioxide insulation layers (liners) with benzocyclobutene (BCB) polymer. The BCB liner TSVs are fabricated by etching deep annular trenches on substrates, void-free filling the trenches with BCB polymer, selective etching the silicon post in the annular trenches, and filling the via with copper. Key fabrication processes including void-free BCB polymer filling in deep trenches, BCB chemical mechanical planarization, and selective etching of silicon post to BCB are developed. TSVs with BCB liners are successfully fabricated and the electrical performance is measured. The measurement results show that the capacitance of the BCB liner TSVs is around 42 fF, and the leakage currents to substrates and to neighboring TSVs are 2.2 pA and 1.1 pA at 10 V voltage, respectively. These preliminary results demonstrate the feasibility of the proposed fabrication technology and the efficacy of BCB liners in reducing TSV capacitance.

Ultralow-Capacitance Through-Silicon Vias With Annular Air-Gap Insulation Layers

Low capacitance is critical to the electric performance of through-silicon vias (TSVs). This paper reports the development and electrical characterization of ultralow-capacitance TSVs which use air gaps to replace the conventional silicon dioxide as the insulation layers. The air-gap TSVs are successfully fabricated by developing a sacrificial technology which uses void-free filling and selective etching of an annular benzocyclobutene polymer cladding that surrounds copper plugs. The capacitance and the leakage current are tested to characterize the electrical performance. The lowest effective dielectric constant of the air enables the capacitance of the air-gap TSVs to be as low as 24 fF, and the capacitance density is more than one order of magnitude lower than that of conventional SiO2 liner TSVs. The leakage current to the substrate is 3 ×10-13 A at 40 V, and no leakage current degradation occurs after a 40-cycle thermal shock test. The preliminary results demonstrate the new air-gap structure and the efficacy of air gaps in reducing TSV capacitance.

Moving Boundary Simulation and Experimental Verification of High Aspect-Ratio Through-Silicon-Vias for 3-D Integration

Because of the pinch-off effect, filling high aspect- ratio, void- and seam-free through-silicon-vias (TSVs) using damascene copper electroplating is one of the technical challenges in realizing 3-D integration and packaging. This paper presents simulation investigation and experimental verification of bottom-up copper electroplating (BCE) to verify its capability in fabricating high aspect-ratio void-free TSVs. Theoretical models for blind- and through-via copper electroplating are derived, and a generic solving method is developed by employing a moving boundary simulation to address the challenge of time-dependent process. The time-resolved evolution of electroplating profiles is simulated after the ion concentration distribution and the electric current density are obtained. The simulation results predict the behaviors of copper electroplating of blind- and through-vias, and reveal the mechanism of void formation. By employing a transfer wafer to provide seed layers, improved BCE is developed and high aspect-ratio void-free TSVs are successfully fabricated. The experimental results verify the theoretical model and the moving boundary simulation method, and prove the capability of BCE in filling high aspect-ratio TSVs.

Thick benzocyclobutene etching using high density SF6/O2 plasmas

Etching of thick nonphotosensitive benzocyclobutene (BCB) was investigated using a high density SF6/O2 plasma with an inductively coupled plasma (ICP) etcher. The effects of SF6 concentration on etching characteristics, including etching rate, anisotropy, and residue, are fully discussed in this article. Moreover, experiments were designed and carried out to study the causes of BCB etching residue. A grasslike etching residue was observed for low SF6 concentration at the bottom of BCB patterns with a SiO2/SixN layer and the BCB patterns cured on a N2-purged hotplate, while residue-free etching is obtained for the BCB patterns cured in a N2-purged vacuum chamber. A high SF6 concentration and exclusion of O2 during hard curing are important to prevent the grasslike etching residue. A highly anisotropic and residue-free etching of thick (∼13 μm) BCB is achieved for BCB cured in a N2-purged vacuum chamber at 250 °C for 1 h and with a pure SF6 plasma under etching conditions of 700 W ICP power, 100 W reactive ...

A Wafer-Level 3D Integration Using Bottom-Up Copper Electroplating and Hybrid Metal-Adhesive Bonding

We report a wafer-level 3D integration scheme using bottom-up copper electroplating (BCE) and hybrid metal-adhesive wafer bonding. Through-silicon-vias (TSVs) with aspect ratio as high as 13 are plated using BCE without forming voids/seams. Cu-Sn bumps electroplated on the TSVs are used together with polymer adhesive for hybrid bonding. A two-layer 3D integration is achieved using BCE and hybrid bonding, validating the feasibility in fabricating wafer-level 3D integration with high aspect ratio TSVs.