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Dive into the research topics where Qianwen Chen is active.

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Featured researches published by Qianwen Chen.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2013

Low Capacitance Through-Silicon-Vias With Uniform Benzocyclobutene Insulation Layers

Qianwen Chen; Cui Huang; Zhimin Tan; Zheyao Wang

Low capacitance is critical to the electric performance of through-silicon-vias (TSVs). This paper reports the development of a low capacitance TSVs by replacing silicon dioxide insulation layers (liners) with benzocyclobutene (BCB) polymer. The BCB liner TSVs are fabricated by etching deep annular trenches on substrates, void-free filling the trenches with BCB polymer, selective etching the silicon post in the annular trenches, and filling the via with copper. Key fabrication processes including void-free BCB polymer filling in deep trenches, BCB chemical mechanical planarization, and selective etching of silicon post to BCB are developed. TSVs with BCB liners are successfully fabricated and the electrical performance is measured. The measurement results show that the capacitance of the BCB liner TSVs is around 42 fF, and the leakage currents to substrates and to neighboring TSVs are 2.2 pA and 1.1 pA at 10 V voltage, respectively. These preliminary results demonstrate the feasibility of the proposed fabrication technology and the efficacy of BCB liners in reducing TSV capacitance.


IEEE Transactions on Electron Devices | 2013

Ultralow-Capacitance Through-Silicon Vias With Annular Air-Gap Insulation Layers

Qianwen Chen; Cui Huang; Dong Wu; Zhimin Tan; Zheyao Wang

Low capacitance is critical to the electric performance of through-silicon vias (TSVs). This paper reports the development and electrical characterization of ultralow-capacitance TSVs which use air gaps to replace the conventional silicon dioxide as the insulation layers. The air-gap TSVs are successfully fabricated by developing a sacrificial technology which uses void-free filling and selective etching of an annular benzocyclobutene polymer cladding that surrounds copper plugs. The capacitance and the leakage current are tested to characterize the electrical performance. The lowest effective dielectric constant of the air enables the capacitance of the air-gap TSVs to be as low as 24 fF, and the capacitance density is more than one order of magnitude lower than that of conventional SiO2 liner TSVs. The leakage current to the substrate is 3 ×10-13 A at 40 V, and no leakage current degradation occurs after a 40-cycle thermal shock test. The preliminary results demonstrate the new air-gap structure and the efficacy of air gaps in reducing TSV capacitance.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2013

Polymer Liner Formation in High Aspect Ratio Through-Silicon-Vias for 3-D Integration

Cui Huang; Qianwen Chen; Zheyao Wang

Replacing silicon dioxide with polymers that have low dielectric constants as the insulation (liner) materials is of great help in reducing the capacitive coupling of throughsilicon-vias and improving the reliability. This paper presents the fabrication of uniform poly propylene carbonate (PPC) polymer liners in high aspect ratio trenches by addressing the difficulty in coating PPC layers on via inner walls. A unique spin-coating method is developed by using vacuum treatment and solvent refill techniques for PPC liner formation for circular and annular trenches. Vacuum treatment and solvent refill facilitate PPC filling in high aspect ratio vias by preventing formation of air bubbles in the vias. By investigating the flow behaviors of PPC precursors and optimizing the spin-coating parameters, an optimal fabrication process is achieved. Using this newly developed technique as well as the optimized processing parameters, uniform PPC liners are successfully fabricated on the inner walls of circular vias with coating aspect ratio greater than 9:1 and the annular vias with filling aspect ratio of 24:1.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2013

Implementation of Air-Gap Through-Silicon-Vias (TSVs) Using Sacrificial Technology

Cui Huang; Qianwen Chen; Dong Wu; Zheyao Wang

Using air-gaps to replace conventional silicon dioxide as the insulators of through-silicon-vias (TSVs) has the possibility to improve the electrical performance and some thermal reliability issues of TSVs. This paper reports the implementation of TSVs with air-gap insulators by developing a polymer sacrificial technology. The sacrificial technology and the key fabrication processes are investigated in detail, including spin-coating of poly propylene carbonate (PPC) on the sidewalls of blind vias, copper chemical-mechanical polishing, PPC grinding, and PPC pyrolysis to form air-gaps. To address the technical challenge in coating thin and conformal PPC sacrificial claddings in blind vias, a vacuum-assisted solvent refilling technique is developed. Air-gap TSVs are successfully fabricated and the electrical performances are characterized. The accumulation capacitance of the air-gap TSVs is 48 fF, and the leakage current is as low as 1.22 pA at bias voltage of 20 V. Finite element simulation shows that air-gaps are able to reduce thermal stresses. The preliminary results demonstrate the feasibility of the sacrificial technology and the good electrical performance of air-gap TSVs.


electronic components and technology conference | 2013

Development of ultra-low capacitance through-silicon-vias (TSVs) with air-gap liner

Qianwen Chen; Cui Huang; Zheyao Wang

This paper presents the development of ultra-low capacitance TSVs using air-gap to replace conventional SiO2 as the insulating liners. Two polymer sacrificial technologies, including Benzocyclobutene (BCB) etching and Propylene Carbonate (PPC) pyrolysis, have been developed to successfully realize the air-gap TSVs. The capacitance-voltage (C-V) characteristics and the leakage current have been measured to evaluate the electrical performances of the air-gap TSVs, and the thermal-mechanical stress has been studies with ANSYS. The measurement results show that the air-gap TSVs have a capacitance density around 0.6 nF/cm2 at the maximum depletion region, and the leakage current is less than 1×10-1 A at 20 V biased voltage, indicating that air-gaps are able to achieve low capacitance and good insulating property. The simulation results show that the air-gap is effective to reduce the thermal stresses in the silicon substrate, which is beneficial for devices performance.


Microelectronic Engineering | 2008

High aspect ratio copper through-silicon-vias for 3D integration

Chongshen Song; Zheyao Wang; Qianwen Chen; Jian Cai; Litian Liu


Microelectronic Engineering | 2013

High aspect ratio and low capacitance through-silicon-vias (TSVs) with polymer insulation layers

Cui Huang; Qianwen Chen; Dong Wu; Zheyao Wang


ECTC | 2011

Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding

Qianwen Chen; Dingyou Zhang; Zheyao Wang; Litian Liu; James J.-Q. Lu


Microelectronic Engineering | 2010

The influence of ultrasonic agitation on copper electroplating of blind-vias for SOI three-dimensional integration

Qianwen Chen; Zheyao Wang; Jian Cai; Litian Liu


Microelectronic Engineering | 2010

Characterization of reactive ion etching of benzocyclobutente in SF6/O2 plasmas

Qianwen Chen; Zheyao Wang; Zhiming Tan; Litian Liu

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Dingyou Zhang

Rensselaer Polytechnic Institute

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James J.-Q. Lu

Rensselaer Polytechnic Institute

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