Zheyao Wang

Low Capacitance Through-Silicon-Vias With Uniform Benzocyclobutene Insulation Layers

Low capacitance is critical to the electric performance of through-silicon-vias (TSVs). This paper reports the development of a low capacitance TSVs by replacing silicon dioxide insulation layers (liners) with benzocyclobutene (BCB) polymer. The BCB liner TSVs are fabricated by etching deep annular trenches on substrates, void-free filling the trenches with BCB polymer, selective etching the silicon post in the annular trenches, and filling the via with copper. Key fabrication processes including void-free BCB polymer filling in deep trenches, BCB chemical mechanical planarization, and selective etching of silicon post to BCB are developed. TSVs with BCB liners are successfully fabricated and the electrical performance is measured. The measurement results show that the capacitance of the BCB liner TSVs is around 42 fF, and the leakage currents to substrates and to neighboring TSVs are 2.2 pA and 1.1 pA at 10 V voltage, respectively. These preliminary results demonstrate the feasibility of the proposed fabrication technology and the efficacy of BCB liners in reducing TSV capacitance.

Ultralow-Capacitance Through-Silicon Vias With Annular Air-Gap Insulation Layers

Low capacitance is critical to the electric performance of through-silicon vias (TSVs). This paper reports the development and electrical characterization of ultralow-capacitance TSVs which use air gaps to replace the conventional silicon dioxide as the insulation layers. The air-gap TSVs are successfully fabricated by developing a sacrificial technology which uses void-free filling and selective etching of an annular benzocyclobutene polymer cladding that surrounds copper plugs. The capacitance and the leakage current are tested to characterize the electrical performance. The lowest effective dielectric constant of the air enables the capacitance of the air-gap TSVs to be as low as 24 fF, and the capacitance density is more than one order of magnitude lower than that of conventional SiO2 liner TSVs. The leakage current to the substrate is 3 ×10-13 A at 40 V, and no leakage current degradation occurs after a 40-cycle thermal shock test. The preliminary results demonstrate the new air-gap structure and the efficacy of air gaps in reducing TSV capacitance.

Air-Gap Through-Silicon Vias

This letter reports for the first time the fabrication and characterization of through-silicon vias (TSVs) using air-gap insulators to enable high-performance 3-D integration. To address the challenge in fabricating extremely high-aspect-ratio air gaps, a CMOS-compatible sacrificial technology based on pyrolysis of poly (propylene carbonate) has been developed, upon which air-gap TSVs have been successfully achieved. The measured capacitance density and leakage current density of air-gap TSVs are 1.22 nF/cm2 and 10 nA/cm2, respectively, about one order and two orders lower in magnitude than TSVs using SiO2 insulators.

Polymer Liner Formation in High Aspect Ratio Through-Silicon-Vias for 3-D Integration

Replacing silicon dioxide with polymers that have low dielectric constants as the insulation (liner) materials is of great help in reducing the capacitive coupling of throughsilicon-vias and improving the reliability. This paper presents the fabrication of uniform poly propylene carbonate (PPC) polymer liners in high aspect ratio trenches by addressing the difficulty in coating PPC layers on via inner walls. A unique spin-coating method is developed by using vacuum treatment and solvent refill techniques for PPC liner formation for circular and annular trenches. Vacuum treatment and solvent refill facilitate PPC filling in high aspect ratio vias by preventing formation of air bubbles in the vias. By investigating the flow behaviors of PPC precursors and optimizing the spin-coating parameters, an optimal fabrication process is achieved. Using this newly developed technique as well as the optimized processing parameters, uniform PPC liners are successfully fabricated on the inner walls of circular vias with coating aspect ratio greater than 9:1 and the annular vias with filling aspect ratio of 24:1.

Implementation of Air-Gap Through-Silicon-Vias (TSVs) Using Sacrificial Technology

Using air-gaps to replace conventional silicon dioxide as the insulators of through-silicon-vias (TSVs) has the possibility to improve the electrical performance and some thermal reliability issues of TSVs. This paper reports the implementation of TSVs with air-gap insulators by developing a polymer sacrificial technology. The sacrificial technology and the key fabrication processes are investigated in detail, including spin-coating of poly propylene carbonate (PPC) on the sidewalls of blind vias, copper chemical-mechanical polishing, PPC grinding, and PPC pyrolysis to form air-gaps. To address the technical challenge in coating thin and conformal PPC sacrificial claddings in blind vias, a vacuum-assisted solvent refilling technique is developed. Air-gap TSVs are successfully fabricated and the electrical performances are characterized. The accumulation capacitance of the air-gap TSVs is 48 fF, and the leakage current is as low as 1.22 pA at bias voltage of 20 V. Finite element simulation shows that air-gaps are able to reduce thermal stresses. The preliminary results demonstrate the feasibility of the sacrificial technology and the good electrical performance of air-gap TSVs.

Moving Boundary Simulation and Experimental Verification of High Aspect-Ratio Through-Silicon-Vias for 3-D Integration

Because of the pinch-off effect, filling high aspect- ratio, void- and seam-free through-silicon-vias (TSVs) using damascene copper electroplating is one of the technical challenges in realizing 3-D integration and packaging. This paper presents simulation investigation and experimental verification of bottom-up copper electroplating (BCE) to verify its capability in fabricating high aspect-ratio void-free TSVs. Theoretical models for blind- and through-via copper electroplating are derived, and a generic solving method is developed by employing a moving boundary simulation to address the challenge of time-dependent process. The time-resolved evolution of electroplating profiles is simulated after the ion concentration distribution and the electric current density are obtained. The simulation results predict the behaviors of copper electroplating of blind- and through-vias, and reveal the mechanism of void formation. By employing a transfer wafer to provide seed layers, improved BCE is developed and high aspect-ratio void-free TSVs are successfully fabricated. The experimental results verify the theoretical model and the moving boundary simulation method, and prove the capability of BCE in filling high aspect-ratio TSVs.

Thick benzocyclobutene etching using high density SF6/O2 plasmas

Etching of thick nonphotosensitive benzocyclobutene (BCB) was investigated using a high density SF6/O2 plasma with an inductively coupled plasma (ICP) etcher. The effects of SF6 concentration on etching characteristics, including etching rate, anisotropy, and residue, are fully discussed in this article. Moreover, experiments were designed and carried out to study the causes of BCB etching residue. A grasslike etching residue was observed for low SF6 concentration at the bottom of BCB patterns with a SiO2/SixN layer and the BCB patterns cured on a N2-purged hotplate, while residue-free etching is obtained for the BCB patterns cured in a N2-purged vacuum chamber. A high SF6 concentration and exclusion of O2 during hard curing are important to prevent the grasslike etching residue. A highly anisotropic and residue-free etching of thick (∼13u2002μm) BCB is achieved for BCB cured in a N2-purged vacuum chamber at 250u2009°C for 1 h and with a pure SF6 plasma under etching conditions of 700 W ICP power, 100 W reactive ...

Thermal Conductivity Enhancement of Benzocyclobutene With Carbon Nanotubes for Adhesive Bonding in 3-D Integration

Thermal management is one of the critical challenges in 3-D integration. The intermediate bonding interfaces between two chips, such as silicon dioxide and polymer adhesives, are the major source of internal thermal resistance in 3-D integrated circuits, leading to thermal issues such as high temperature spots and larger temperature gradients. This paper reports an approach to reduce the thermal resistance of a common bonding adhesive benzocyclobutene (BCB) by loading carbon nanotubes (CNTs) to improve the thermal conductivity. By exploiting the aromatic property of BCB, an ultrasonication-assisted noncovalent dispersion method is developed to disseminate CNTs with different concentrations into BCB. Thanks to the high thermal conduction ability of CNTs, the thermal conductivity of BCB is improved as much as 20% by loading 1.5 wt% CNTs. The surface temperature of bonded chips during heating are measured to evaluate the dynamic heat transfer ability, and a 13% improvement is achieved for BCB-CNT composites. The bonding strength of pure BCB and BCB-CNT composites are tested and the results show that CNTs is beneficial to improving the bonding strength.

Thermal and Electrical Reliability Tests of Air-Gap Through-Silicon Vias

Through-silicon vias (TSVs) with air gaps as the isolators have been developed to reduce the TSV capacitance and to solve the reliability problems associated with thermomechanical stresses. This paper reports the reliability assessment of the air-gap TSVs by measuring the C-V, I-V, and resistance of the TSVs in terms of thermal and electrical stresses with a focus on thermal shock, temperature variations, and voltage ramps. Thermal shock tests are performed to evaluate the insulation capability and the thermomechanical stability of the air gaps. Temperature variations are implemented to investigate the influences of high temperatures on the electrical characteristics of the air-gap TSVs. Voltage ramp tests are carried out, and the time-dependent dielectric breakdown is obtained to evaluate the integrity of the air gaps and the intrinsic barrier capability. The preliminary results show that the air-gap TSVs have good thermal stability, excellent dielectric property, and satisfactory structure and barrier stability.

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

Through-silicon vias (TSVs) using benzocyclobutene (BCB)-liners as the insulator have the potential for reducing the TSV capacitances and the thermal expansion stresses. This paper reports the assessments of BCB-liner TSVs with respect to thermal and electrical properties. The C-V and I-V characteristics are measured at room temperature and at an elevated temperature as high as 125°C to characterize the electrical properties of capacitance and leakage current at different temperatures. Some C-V and I-V features associated with BCB-liners are discussed and the mechanisms are analyzed. Thermal cycling between -65°C and 150°C is performed, and the C-V and I-V characteristics are measured before and after thermal cycling to evaluate the thermomechanical stability of the BCB-liners, and the results show that the C-V and I-V properties are improved after thermal cycling. These preliminary results on the electrical and thermal properties of BCB-liner TSVs show that they have good thermal stability.