Zhiqun Li

A 2.4 GHz Ultra-Low-Power Current-Reuse CG-LNA With Active

An ultra-low-power common-gate low noise amplifier (CG-LNA) for 2.4 GHz wireless sensor network (WSN) applications is proposed in this letter. The current-reuse and active gm-boosting techniques are utilized. The analysis, design method and measurement results are shown. An implemented prototype using 0.18 μm CMOS technology is evaluated using on-wafer probing. Measurements also show a gain of 14.7 dB and an IIP3 of 2 dBm at 2.44 GHz. The measured noise figure is 4.8 dB at 2.44 GHz. S11 is below -18 dB from 2-3 GHz. The proposed LNA consumes 0.58 mW from 1.8 V dc supply.

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A 5th-order Chebyshev active RC complex filter for wireless sensor networks with automatic frequency tuning is presented in this paper. This filter is synthesized from 5th-order low-pass LC prototype, and designed using leapfrog structure. An automatic frequency tuning is used to prevent the deviation of the RC constant of the filter. This filter is fabricated in TSMC 0.18μm CMOS process. The measurement results show that the passband gain of the filter is about 16dB and the ripple in the passband is about 1.5dB. It is centered at 2MHz with 2.45MHz of bandwidth after tuning. The image rejection ratio (IRR) is about 40dB and the adjacent channel rejuction (ACR) around 6MHz is about 55dB. The precision of the tuning system could be controlled to less than 3%. The filter consumes about 6.5mA totally with 1.8V power supply.

-Boosting Technique

This paper proposed an X-band 6-bit passive phase shifter (PS) designed in 0.18 μ m silicon-on-insulator (SOI) CMOS technology, which solves the key problem of high integration degree, low power, and a small size T/R module. The switched-topology is employed to achieve broadband and flat phase shift. The ESD circuit and driver are also integrated in the PS. It covers the frequency band from 7.5 to 10.5 GHz with an EMS phase error less than 7.5°. The input and output VSWRs are less than 2 and the insertion loss (IL) is between 8-14 dB across the 7.5 to 10.5 GHz, with a maximum IL difference of 4 dB. The input 1 dB compression point (IP 1dB ) is 20 dBm.

A 5 th -order Chebyshev active RC complex filter with automatic frequency tuning for wireless sensor networks application

This study was initiated to design a low noise amplifier (LNA), which could work with ultra low voltage of 0.5V and was optimized for WSN application using SMIC 0.13μm RF-CMOS technology. The topology of differential inductance degenerated folded cascode based on power-constrained simultaneous noise and input matching (PCSNIM) technique was adopted. Chosen circuit demonstrated a power gain of 16.5dB, consuming 3.3mW DC power, showing 0.78dB NF and an input 1-dB compression point of −20.9dBm. Both input match (S11) and output match (S22) were below −19dB. The results indicate that this LNA is fully applicable to the low voltage and low power application.

A high linearity X-band SOI CMOS digitally-controlled phase shifter

This letter presents a wideband transformer balun with a center open stub. Since the interconnected line between two coupled-lines greatly deteriorates the performance of balun in millimeter-wave designs, the proposed center open stub provides a good solution to further optimize the balance of balun. The proposed transformer balun with center open stub has been fabricated in 90 nm CMOS technology, with a compact chip area of 0.012 mm2. The balun achieves an amplitude imbalance of less than 1 dB for a frequency band ranging from 1 to 48 GHz along with a phase imbalance of less than 5 degrees for the frequency band ranging from 2 to 47 GHz.

A 0.5V CMOS LNA for 2.4-GHz WSN application

The balance compensating techniques for asymmetric Marchand balun are presented in this letter. The amplitude and phase difference are characterized explicitly by S21 and S31, from which the factors responsible for the balance compensating are determined. Finally, two asymmetric Marchand baluns, which have normal and enhanced balance compensation, respectively, are designed and fabricated in a 0.18 μm CMOS technology for demonstration. The simulation and measurement results show that the proposed balance compensating techniques are valid in a very wide frequency range up to millimeter-wave (MMW) band.

A Wideband Transformer Balun With Center Open Stub in CMOS Process

This paper presented a 12-channel parallel optical receiver front-end amplifier array design and realization in a low cost 0.18 µm CMOS technology. Each channel incorporated a transimpedance amplifier and a limiting amplifier. To meet the challenge for the design of high gain front-end amplifier at date rate of up to 10 Gb/s, an optimized circuit topology was proposed and some bandwidth extension technologies were adopted, including regulated cascode, shunt peaking, and active negative feedback. Against the power consumption, crosstalk and noise, some corresponding solutions were presented such as applying isolation structure for parallel amplifier array, and optimization of noise and circuit parameters for 10 Gb/s applications. The on-wafer measurements revealed that this chip’s operation speed reached up to 10 Gb/s per channel, and 120 Gb/s with 12-channel in parallel operation. Consuming a DC power of 853 mW from a 1.8 V supply voltage, the chip exhibits a conversion gain of up to 92.6 dBΩ, and a −3 dB bandwidth of 8 GHz, the output swing and input sensitivity for a bit-error rate of 10−12 at 10 Gb/s are 310 mV and 10 mVpp, respectively. The chip size is 1142 µm×3816 µm including on-wafer testing pads.

Balance-Compensated Asymmetric Marchand Baluns on Silicon for MMICs

A 10-Gb/s inductorless limiting amplifier for optic-fiber transmission system is designed and fabricated in a 0.18-μm CMOS technology. The whole circuit consists of an input buffer, three broadband gain stages, an output buffer for driving 50-Ω transmission lines and a DC offset cancellation circuit. By employing a third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Consuming a DC power of 72 mW from a 1.8-V supply voltage, this limiting amplifier exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 8.6 GHz, and it allows an input dynamic range of at least 40 dB. With a pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity are about 350 mVpp and 10 mVpp, respectively. Due to the absence of the spiral inductors, the chip size of this limiting amplifier including the pads is 0.58 × 1.06 mm², where the active circuit area only occupies 285 × 600 μm².

A 12×10 Gb/s fully integrated CMOS parallel optical receiver front-end amplifier array

A 10-Gb/s transimpedance amplifier (TIA) for the parallel optical receiver module is realized in 0.18-μm CMOS technology. The proposed TIA employs a regulated cascode (RGC) input structure and adopts active inductor peaking and feedback techniques to enhance the bandwidth. Besides, a noise optimization is processed. The TIA provides a conversion gain of 50 dBΩ and 3-dB bandwith of 7 GHz. The measured sensitivity is about 35 μA at a bit error rate of 10⁻¹² with a 2³¹−1 pseudorandom test pattern for 10 Gb/s operation. Under a 1.8-V supply voltage, the differential TIA consumes 29.2 mW, counting an output buffer. The core chip area is 144×160 μm² excluding the output buffer and testing pads.

A 10-Gb/s Inductorless CMOS Limiting Amplifier for Optic-Fiber Transmission System

This paper presents a novel low noise amplifier (LNA) topology with image rejection (IR), called IRLNA. It achieves a high IR ratio using on-chip inductors with low quality factor. Two IRLNAs based on a standard 0.18-/spl mu/m CMOS technology are designed with L- and /spl pi/- resonant network, respectively. They have the same power consumption of 8 mW with one 1.8 V power supply. At the signal frequency of 5.25 GHz in the band of WLAN 802.11a, and with the image frequency at 3.25GHz, the simulation results show that the IR ratios achieve 71dB for L-resonant network and 92dB for /spl pi/-resonant network with on-chip inductors, and their noise figures are 1.4 dB and 1.7 dB, respectively.