Amir Ghaffari

Tunable N-Path Notch Filters for Blocker Suppression: Modeling and Verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50-Ω environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4-2.8 dB. The rejection at the notch frequency is 21-24 dB, P1 dB > +2 dBm, and IIP3 > +17 dBm.

A differential 4-path highly linear widely tunable on-chip band-pass filter

A passive switched capacitor RF band-pass filter with clock controlled center frequency is realized in 65nm CMOS. An off-chip transformer which acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant −3dB bandwidth of 35MHz and can be tuned from 100MHz up to 1GHz. IIP3 is better than 19dBm, P1dB=2dBm and NF≪5.5dB at Pdiss=2mW to 16mW.

A 4-Element Phased-Array System With Simultaneous Spatial- and Frequency-Domain Filtering at the Antenna Inputs

To reject strong interference in excess of 0 dBm, a 4- element LO-phase shifting phased-array receiver with 8-phase passive mixers terminated by baseband capacitors is presented. The passive mixers upconvert both the spatial and frequency domain filtering from baseband to RF, hence realizing blocker suppression directly at the antenna inputs. A comprehensive mathematical model provides a set of closed-form equations describing the spatial and frequency domain filtering including imperfections. A prototype is realized in 28 nm CMOS. It exploits third harmonic reception to achieve a wide RF-frequency range from 0.6-4.5 GHz at 34-119 mW power dissipation, while also providing impedance matching. Out of the band/beam, a 1 dB-compression point as high as +12/+10 dBm has been measured. The 1-element noise figure over the RF-frequency range is 4-6.3 dB, while in-beam/band IIP3 values of 0- +2.6 dBm are measured. This proposed technique can be instrumental to make RF receivers more robust for interference, while still being flexibly tunable in frequency.

Simultaneous spatial and frequency-domain filtering at the antenna inputs achieving up to +10dBm out-of-band/beam P 1dB

Multi-antenna transceivers with beam-forming are recently gaining interest for low GHz frequencies (<;6GHz) [1-4]. In the antenna beam, (phase-shifted) signals from multiple antennas add constructively, improving SNR, while out-of-beam signals add destructively (i.e. spatial filtering). Usually the summation point is behind some gain blocks, which then need to be capable of handling strong signals. To improve the input-referred compression point P1dB, a fully passive switched-capacitor approach was presented in [4], providing P1dB=+2dBm, but at a high noise penalty: NF=18dB. Here we propose to sum immediately at the baseband capacitors of passive mixer-first switched-RC downconverters. We show that this can render a direction-dependent RF impedance (spatial filtering) together with RF bandpass frequency filtering at lower noise and higher P1dB.

A 100–800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving

Radio transceivers capable of dynamic spectrum access require frequency-agile transmitters with a clean output spectrum. High- Q filters are difficult to implement on chip and have limited tuning range. Transmitters with high linearity and broadband harmonic rejection can be more flexible and require less filtering. However, traditional harmonic rejection mixers suppress only a few harmonics. This paper presents an 8-path polyphase transmitter, which exploits mixer-LO duty-cycle control and a tunable first-order RC low-pass filter to suppress ALL harmonics to below -40 dBc. The optimum duty-cycle theoretically is 43.65% and a resolution of better than 0.1% is required to keep the spread in harmonic rejection within 1 dB. We propose a simple monotonic duty-cycle control circuit and show by design equations and measurements that it achieves the required resolution over three octaves of frequency range. Also, analysis indicates that LO duty-cycle reduction compared with 50% improves power upconverter efficiency. A transmitter realized in 0.16- μm CMOS works from 100 to 800 MHz at a maximum single-tone output power of 10.8 dBm with an efficiency of 8.7%, outperforming previous designs. The OIP3 is >21 dBm, while the LO leakage and image rejection is better than -45 dBc.

40 dBc for ALL Harmonics

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3-1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth.

A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and −169 dBm/Hz DANL

Integration of digital RF transmitters and digital power amplifiers (DPA) is becoming of great interest for systems-on-chip (SoCs) available in nanometer technologies [1]. Small and high-speed switching devices directly benefit switching power amplifiers in achieving peak power with high peak efficiency. However PA back-off efficiency remains a big challenge in high-data-rate systems with large peak-to-average ratio (PAR) such as in WLAN. Different solutions have been published to enhance power backoff efficiency but at a cost of higher complexity and larger area [2,3].